3D Semiconductor Stacking via Wafer Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices scale to smaller sub-micron sizes, it becomes challenging to increase device density and complexity in manufacturing, particularly due to limitations in 2D transistor density scaling and wire pitch scaling issues such as resistance, capacitance, and reliability, which hinder the integration of more transistors into circuits.
Innovation Solution
A 3D semiconductor apparatus is formed by stacking wafers with high mobility channels using optimized substrates and nano plane materials, where a first portion with NMOS and PMOS devices is bonded to a second portion with differently grown channel regions, using a carrier substrate and dielectric layers to align and connect the devices, allowing for increased device density and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2D transistor scaling is continued to increase device density, then the number of transistors per unit area increases, but wire pitch scaling issues such as resistance, capacitance, and reliability worsen
Solution Approach 1:
The patent transitions from 2D planar transistor arrangement to 3D vertical stacking, where multiple transistor layers are stacked along the Z-direction. This dimensional change allows continued increase in transistor density without further reducing wire pitch in the plane, thereby avoiding the reliability issues associated with sub-micron wire scaling
2Productivity
If device dimensions are scaled to smaller sub-micron sizes, then production efficiency increases and costs decrease, but manufacturing complexity increases
Solution Approach 1:
The patent divides the semiconductor device into multiple discrete layers or stacks that are formed separately and then integrated through bonding. This segmentation allows each layer to be manufactured using optimized processes, reducing overall manufacturing complexity while maintaining high production efficiency
Solution Approach 2:
By moving to 3D vertical stacking, the patent enables parallel processing of multiple transistor layers simultaneously, increasing production efficiency without proportionally increasing manufacturing complexity
3Ease of manufacture
If 2D circuit fabrication is used to create transistors in one plane, then manufacturing process simplicity is maintained, but device density increases are limited
Solution Approach 1:
The patent extends fabrication from 2D planar processing to 3D vertical stacking, maintaining relative process simplicity while achieving higher transistor density through the addition of the vertical dimension. Multiple transistor stacks are formed using similar fabrication steps repeated in different vertical positions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher device density and performance by overcoming scaling limitations, increasing the number of transistors per unit area and enhancing transistor density through vertical stacking, thus advancing semiconductor roadmap and manufacturing efficiency.
Implementation Method 1
A carrier substrate can be attached to the second portion of the semiconductor apparatus
Implementation Method 2
The bulk substrate material can be removed from the second substrate
Implementation Method 3
The first portion and the second portion can be bonded to form the semiconductor apparatus
Data Source
AI summary
Aspects of the disclosure provide a method of forming a semiconductor apparatus including a first portion and a second portion. The first portion is formed on a first substrate and includes at least one first semiconductor device. The second portion is formed on a second substrate including a bulk substrate material and includes at least one second semiconductor device. A carrier substrate is attached to the second portion. The bulk substrate material is removed from the second substrate. The first portion and the second portion are bonded to form the semiconductor apparatus where the at least one second semiconductor device is stacked above the at least one first semiconductor device along a Z direction substantially perpendicular to a substrate plane of the first substrate. The at least one first semiconductor device and the at least one second semiconductor device are positioned between the carrier substrate and the first substrate.