3D Semiconductor Fabrication Stepped Etching Process
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high complexity and cost of fabricating three-dimensional semiconductor devices are hindered by the need for numerous patterning processes, which increase as the number of stacked horizontal layers grows, making it challenging to achieve high integration density while maintaining cost-effectiveness and reliability.
Innovation Solution
A method involving the formation of a stack structure with a stepped structure in the contact region, achieved by sequentially stacking horizontal layers and performing specific etching processes with different depths, followed by repeated shrinking of mask patterns to reduce the number of photolithography and etching processes, thereby simplifying the fabrication process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of stacked horizontal layers is increased to achieve high integration density, then the integration density is improved, but the number of patterning processes increases making the fabrication process more complex
Solution Approach 1:
The fabrication process is segmented into two distinct etching stages: a first etching process that etches to a first depth to form initial stepped structures, and a second etching process that etches to a second depth (greater than the first depth) to form final stepped structures. This segmentation allows complex 3D patterns to be created through controlled sequential removal of material at different depths, reducing the number of photolithography steps required compared to conventional approaches.
Solution Approach 2:
The invention transitions from conventional two-dimensional planar patterning to three-dimensional stepped patterning by utilizing vertical depth as an additional dimension. The mask patterns define openings that extend in one direction, and etching processes create stepped structures with different depths, enabling complex 3D semiconductor device architectures to be formed without proportionally increasing the number of patterning processes.
2Ease of manufacture
If conventional two-dimensional planar semiconductor memory devices are used, then the fabrication process is simpler, but the integration density is limited by planar area
Solution Approach 1:
The invention moves from two-dimensional planar structures to three-dimensional stepped structures by introducing vertical depth variation through controlled etching processes. The stack structure includes horizontal layers with different etch depths creating stepped configurations, allowing integration density to increase in the vertical dimension while maintaining fabrication process simplicity through the use of mask patterns that cover the cell array region and expose specific portions for selective etching.
3Productivity
If three-dimensional semiconductor memory devices are fabricated using conventional methods, then integration density is improved, but the cost per bit increases and reliability may be compromised
Solution Approach 1:
The fabrication process is divided into systematic stages with the first etching process creating initial stepped structures and the second etching process completing the final stepped structures. This segmented approach provides process control and repeatability, reducing manufacturing variability and improving reliability while maintaining cost-effectiveness through efficient use of etching steps rather than requiring an equivalent number of photolithography processes.
Solution Approach 2:
The mask patterns are formed with specific configurations that preliminarily define the regions to be etched at different depths. The first mask pattern defines openings extending in one direction, and the second mask pattern exposes specific portions, allowing the etching processes to proceed with predetermined precision. This preliminary masking action ensures consistent stepped structure formation across multiple devices, improving yield and reducing cost per bit.
Data Source
AI summary
According to example embodiments of inventive concepts, a method of fabricating a 3D semiconductor device may include: forming a stack structure including a plurality of horizontal layers sequentially stacked on a substrate including a cell array region and a contact region; forming a first mask pattern covering the cell array region and defining openings extending in one direction over the contact region; performing a first etching process with a first etch-depth using the first mask pattern as an etch mask on the stack structure; forming a second mask pattern covering the cell array region and exposing a part of the contact region; and performing a second etching process with a second etch-depth using the second mask pattern as an etch mask structure on the stack structure. The second etch-depth may be greater than the first etch-depth.