3D Semiconductor Device Vertical Integration via Segmented Channel Holes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Three-dimensional (3D) semiconductor devices face reliability issues compared to two-dimensional (2D) devices, necessitating improvements in their manufacturing processes to enhance integration and performance.
Innovation Solution
A method of manufacturing a 3D semiconductor device involving the formation of a multilayered structure with alternately stacked material layers, etch stop patterns, channel holes, channel layers, insulating layers, and impurity-doped layers, along with recessed regions and interlayer dielectric layers, to improve device reliability and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are reduced in size to increase integration degree, then the integration degree of memory cells is increased within a limited space, but physical limitations are reached that prevent further size reduction
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional structure by forming vertical channel holes through stacked material layers. This dimensional change allows memory cells to be arranged in the vertical direction (z-axis) in addition to the horizontal plane, significantly increasing integration density without further reducing individual cell size.
2Quantity of substance
If three-dimensional semiconductor device structure is formed to increase integration degree, then area of semiconductor substrate is efficiently used and integration degree is increased, but reliability of the device decreases compared to two-dimensional devices
Solution Approach 1:
The patent divides the three-dimensional structure into discrete, uniformly formed channel holes through the stacked material layers. Each channel hole represents a segmented memory cell unit with consistent dimensions and positioning, allowing reliable fabrication and operation despite the vertical complexity of the 3D architecture.
3Reliability
If uniformity in recessed regions and impurity-doped layers is ensured to improve operating characteristics, then reliability and integration are enhanced, but manufacturing process complexity increases
Solution Approach 1:
The patent forms the multilayered structure of alternating first and second material layers before creating the channel holes. This preliminary stacking of layers with different etch characteristics enables subsequent uniform etching processes to automatically produce consistent channel hole depths and recessed region uniformity, improving reliability while managing manufacturing complexity through process integration.
Data Source
AI summary
A three-dimensional (3D) semiconductor device includes first interlayer dielectric layers and word lines that are alternately stacked on a substrate; select lines formed on the first interlayer dielectric layers and the word lines; etch stop patterns formed on the select lines to contact the select lines; channel holes formed to pass through the select lines, the first interlayer dielectric layers, and the word lines; channel layers formed on surfaces of the channel holes; insulating layers formed in the channel holes, the insulating layers having an upper surface that is lower than upper surfaces of the etch stop patterns; impurity-doped layers formed in channel holes on upper surface of the insulating layers; and a second interlayer dielectric layer formed over the etch stop patterns and the impurity-doped layers.