3D Semiconductor Device Vertical Stacking for Integration Density
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Solution Overview
Problem
As semiconductor devices are scaled down, their operating characteristics deteriorate due to high integration, leading to challenges in achieving superior performance and increased integration.
Innovation Solution
The development of three-dimensional semiconductor devices with vertically stacked transistors and innovative contact structures, including active regions, gate electrodes, and metal layers, which allow for increased integration and reduced cell height, enabling more efficient signal transfer and routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional device layout is used, then manufacturing is simpler, but integration is limited and cell area is large
Solution Approach 1:
The patent transitions from two-dimensional device layout to three-dimensional vertically stacked transistors. Multiple active regions (first active region, second active region) are stacked vertically with corresponding gate electrodes and channel patterns, enabling increased integration density without compromising manufacturing feasibility through established semiconductor processing techniques
2Ease of operation
If two-dimensional device layout is used, then routing is simpler, but routing freedom is limited and cell area is large
Solution Approach 1:
The patent implements multi-layer metal structures (first metal layer, second metal layer, third metal layer) with vertical vias and horizontal wiring, creating three-dimensional routing paths. This vertical stacking of metal layers and routing channels provides enhanced routing freedom and connectivity options while maintaining manageable complexity through systematic layer organization
3Productivity
If device size is scaled down, then integration increases, but operating characteristics deteriorate
Solution Approach 1:
The patent employs vertically stacked transistors where multiple active regions are arranged in the vertical direction rather than horizontally scaling down individual transistors. This three-dimensional configuration increases integration density while maintaining adequate transistor dimensions for proper operating characteristics, as each stacked transistor can retain sufficient channel width and length
4Productivity
If vertical stacking is implemented, then integration increases and cell height reduces, but device complexity increases
Solution Approach 1:
The patent divides the device into distinct vertical segments including first active region with first gate electrode, second active region with second gate electrode, and corresponding metal layers. Each segment is independently structured with source/drain patterns, channel patterns, and gate electrodes, allowing modular fabrication and reducing overall structural complexity through systematic segmentation
Data Source
AI summary
Disclosed are three-dimensional semiconductor device and their fabrication methods. The device includes a first active region on a substrate and including a first source/drain pattern and a first channel pattern connected to the first source/drain pattern, a first active contact on the first source/drain pattern, a second active region on the first active region and the first active contact and including a second source/drain pattern and a second channel pattern connected to the second source/drain pattern, a second active contact on the second source/drain pattern, a gate electrode that vertically extends from the first channel pattern toward the second channel pattern, a first power line and a second power line that are below the first active region, and a first metal layer on the gate electrode and the second active contact.