Nanoinformatics TRIZ Cases
- Nanowire Channel Fabrication via Hybrid Growth and Transfer
A hybrid process grows nanowires vertically then transfers them horizontally for precise gate alignment.
- Organic Semiconductor Nanocomposite Electrodes for Low Contact Resistance
Homogeneous organic semiconductor electrodes with carbon nanoparticles eliminate Schottky barriers to lower contact resistance and boost charge mobility.
- Imprint Lithography Ink Composition for Pattern Transfer
Optimized polymer resin and tackifier ratios minimize blanket contamination while maintaining high pattern transfer accuracy.
- Photovoltaic Cell Macromolecular Active Layer Excitation Energy
Macromolecular compound active layer absorbs longer wavelength light to enhance photoelectric conversion efficiency in photovoltaic cells.
- Diblock Copolymer Mask for MRAM MTJ Uniformity
Template-registered diblock copolymer mask creates uniform features down to 10 nm dimensions via self-assembly.
- Reference Point Mark with Upright Walls for EUV Reflective Mask
Upright side walls on the reference point mark preserve detection contrast through stacked layers, resolving dust accumulation issues in deep recesses.
- Interlayer PCBM Polymerization for Photoelectric Device Fabrication
UV-Ozone treatment polymerizes the interlayer PCBM to reduce solubility, preventing dissolution during processing and improving yield rates.
- Imprint Apparatus Gap Control for Replacement Gas Reduction
Dynamic gap adjustment between the mold and substrate minimizes replacement gas volume while maintaining pattern quality and preventing air bubbles.
- Porous Nano-Imprint Lithography Templates for Gas Diffusion
Mesoporous oxide layers in nano-imprint lithography templates enable trapped gas escape, resolving pattern distortion and improving feature fidelity.
- Bottom Dielectric Isolation for Semiconductor Gate Stability
Continuous BDI and STI liners support fin stacks during fabrication, preventing gate collapse from high germanium oxidation.
- Air Spacer in GAA Transistor Gate Structure
Replacing solid dielectric with an air spacer reduces parasitic capacitance, enhancing performance of gate-all-around transistor devices.
- Imprint Lithography Template Defect Detection via Exclusion Zones
An imaging system identifies exclusion zones created by particles on imprint templates to enable real-time defect detection.
- Quantum Dot Devices With Patterned Gates And Curved Spacers
Patterned gates with curved spacers shape quantum dot potential wells for precise spatial localization of qubits.
- Imprint Mold Release Layer Cleaning via Light Irrigation
Light irradiation reduces the water contact angle of an imprint mold release layer before alkali cleaning.
- Nanocrystal Memory Device Manufacturing via Precursor Self-Assembly
Precursor self-assembly controls nucleation spacing to eliminate random agglomeration, ensuring consistent threshold voltages across semiconductor wafers.
- Thermal Embossing of Reflowed Resist Lenses for Aspheric Master Wafers
A photo-patternable polymer substrate forms isolated sections that reflow into uniform hemispheres before precision diamond stamping creates aspheric lens shapes.