Nanostructure FET Gate Alignment via Embedded Catalyst
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Solution Overview
Problem
Current technologies face challenges in precisely positioning nanostructures like carbon nanotubes or semiconducting nanowires within high layout density silicon CMOS technology, which is essential for effective switching devices.
Innovation Solution
The method involves forming a field effect transistor (FET) with nanostructure channels by using pre-patterned, embedded catalyst lines and a replacement gate process, where catalyst particles are precisely positioned to grow nanostructures self-aligned to the gate, eliminating the need for separate placement and growth of nanostructures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If nanostructures are synthesized by conventional methods (arc discharge, laser ablation, CVD), then large quantities of nanotubes can be produced, but precise positioning and placement of the nanostructures becomes difficult
Solution Approach 1:
The patent applies preliminary action by pre-forming source/drain layers and gate structures before growing the nanostructures. The catalyst layers are deposited and patterned in advance, and the gate is formed beforehand to serve as a reference structure. This allows nanostructures to be grown in predetermined locations with precise positioning relative to the gate, eliminating the need for post-growth placement while maintaining high production quantities.
Solution Approach 2:
The patent uses catalyst layers as intermediary structures that mediate between the source/drain layers and the final nanostructures. The catalyst layers are deposited, patterned, and embedded within the source/drain structure, serving as controlled growth sites. This intermediary approach enables precise positioning of nanostructures at specific locations between source and drain regions while allowing continuous growth processes to produce large quantities.
2Adaptability or versatility
If nanostructures are precisely positioned for high layout density, then compatibility with silicon CMOS technology improves, but the complexity of the fabrication process increases
Solution Approach 1:
The patent merges multiple fabrication steps into integrated processes. The source/drain layers and catalyst layers are deposited and patterned together in a unified sequence. The gate formation is combined with the nanostructure growth process, where the pre-formed gate serves as the reference for positioning catalyst layers and subsequent nanostructure growth. This merging reduces the number of separate alignment and placement steps, simplifying the overall process while achieving precise positioning for CMOS compatibility.
Solution Approach 2:
The patent applies self-service through self-aligned fabrication processes. The pre-formed gate automatically serves as the alignment reference for depositing and patterning catalyst layers. The catalyst layers are positioned relative to the gate structure itself, and the nanostructures grow from these catalyst sites in predetermined locations. This self-alignment eliminates the need for separate lithographic alignment steps, reducing process complexity while ensuring precise positioning for high layout density CMOS integration.
3Manufacturing precision
If separate placement and growth of nanostructures is performed, then positioning control is improved, but the number of fabrication steps increases
Solution Approach 1:
The patent applies preliminary action by pre-forming the gate structure and source/drain layers with embedded catalyst layers before growing the nanostructures. The catalyst layers are deposited and patterned in advance at precise locations, and the gate is formed beforehand to serve as an alignment reference. This preliminary preparation enables controlled positioning without requiring separate placement steps, as the nanostructures grow directly from the pre-positioned catalyst sites in a single continuous growth process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the precise formation of FETs with nanostructure channels, enhancing compatibility with high layout density CMOS technology and improving the positioning and growth of nanostructures, thereby enabling their effective utilization in switching devices.
Implementation Method 1
growing nanostructures between the source and the drain from the catalyst sites
Data Source
AI summary
A field effect transistor (FET) includes a drain formed of a first material, a source formed of the first material, a channel formed by a nanostructure coupling the source to the drain, and a gate formed between the source and the drain and surrounding the nanostructure.