Nonvolatile Memory Device With Segmented Gate Structure
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Solution Overview
Problem
Conventional nonvolatile memory devices using nano crystals face limitations in scaling down due to threshold voltage shifts and reliability issues, particularly when trying to achieve multi-bit storage without increasing device size, leading to errors and reduced integration.
Innovation Solution
The method involves forming a nonvolatile memory device with a nano-sized charge storage layer, including a tunnel insulating layer, a charge storage layer of amorphous silicon, and a blocking insulating layer, and using a middle gate and side gates to improve integration and reliability, allowing for stable injection of electrical charges and multi-bit operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the memory device is scaled down to increase integration, then device size is reduced, but threshold voltage shifts and reliability issues occur
Solution Approach 1:
The gate structure is segmented into a middle gate and two side gates, allowing independent control and optimization of each gate component. This segmentation enables better voltage control and reduces threshold voltage shifts while maintaining scaled-down device dimensions, thereby improving reliability without sacrificing integration density.
Solution Approach 2:
Different regions of the gate structure are assigned different functions: the middle gate controls the main channel while the side gates control the source and drain regions. This local differentiation allows optimized voltage application in each region, reducing unwanted threshold voltage shifts and improving operational reliability at scaled dimensions.
2Quantity of substance
If electrical charges are injected close to source/drain regions to achieve multi-bit operation, then storage capacity is increased, but lateral diffusion causes disturbance and errors
Solution Approach 1:
The gate is divided into middle and side gates that can be independently controlled. The side gates are specifically positioned to confine electrical charges in the charge trap layer, preventing lateral diffusion toward source and drain regions. This enables multi-bit storage through controlled charge injection while maintaining operational reliability by preventing charge disturbance.
Solution Approach 2:
The side gates act as intermediary structures between the charge injection region and the source/drain regions. By applying appropriate voltages to the side gates, the electrical charges are confined in the charge trap layer and prevented from laterally diffusing to the source and drain regions, thus enabling reliable multi-bit operation.
3Reliability
If channel length is maintained at more than a given length to prevent charge diffusion, then reliability is improved, but integration density is reduced
Solution Approach 1:
The gate structure is segmented into a middle gate and two side gates positioned at different locations along the channel. This segmentation allows the channel length to be shortened for higher integration density while the side gates provide additional control to prevent charge diffusion, thereby maintaining operational reliability without sacrificing productivity.
Solution Approach 2:
The gate control is extended from a single-dimensional middle gate to include side gates positioned laterally adjacent to the channel. This dimensional expansion allows effective charge confinement and reliability control even with shorter channel lengths, enabling higher integration density without compromising operational reliability.
Data Source
AI summary
Example embodiments relate to a semiconductor memory device and methods of forming the same. Other example embodiments relate to a nonvolatile memory device and methods of forming the same. The memory device may include memory cells separately formed on a channel region between impurity regions formed on a substrate. The memory cells may each include a memory layer having a tunnel insulating layer, a nano-sized charge storage layer, and a blocking insulating layer and a side gate formed on the memory layer. According to example embodiments, larger scale integration of the nonvolatile memory devices may be achieved and the reliability of the memory devices may increase.