Bottom Dielectric Isolation for Semiconductor Gate Stability
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Solution Overview
Problem
As semiconductor device downscaling approaches the 5 nanometer threshold, the formation of bottom dielectric isolation (BDI) regions in field effect transistors (FETs) faces challenges such as oxidation of high Ge concentration layers during shallow trench isolation, leading to structural weaknesses and mechanical instability of gate structures, which can result in BDI air gaps and gate collapse.
Innovation Solution
The formation of BDI regions is initiated at an early fabrication stage with continuous BDI and STI liner structures, and multiple dielectric portions are formed under fin or nanosheet channel edges to provide mechanical stability, supporting the fin or nanosheet stack during BDI formation, using methods that include selective removal of a high Ge concentration sacrificial layer and deposition of a low-k dielectric spacer material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a high Ge concentration sacrificial layer is used to form BDI regions, then the BDI regions can be formed by selective removal, but oxidation occurs during shallow trench isolation leading to structural weaknesses and mechanical instability
Solution Approach 1:
The patent uses a sacrificial layer made of semiconductor material with high germanium concentration that is intentionally designed to be temporary and removable. This sacrificial layer is deposited on the substrate, then removed through selective etching to create the BDI region. The sacrificial nature of this layer allows precise BDI formation without the oxidation problems that would occur with permanent high-Ge structures during STI processing.
2Strength
If continuous BDI and STI liner structures are formed early in fabrication, then mechanical stability is enhanced, but the process complexity increases
Solution Approach 1:
The patent combines the BDI liner and STI liner into a single continuous liner structure that is formed simultaneously in one deposition process. This continuous liner provides uninterrupted mechanical support from the substrate through the BDI region and into the STI regions, enhancing overall structural stability. By merging these two liner functions into one process step rather than forming them separately, the patent reduces fabrication complexity while achieving the mechanical stability benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances mechanical stability and suppresses leakage currents between source and drain regions, maintaining structural integrity and reducing adverse device artifacts like oxidation and undercutting issues.
Implementation Method 1
deposition of a low-k spacer material in place of the sacrificial layer
Implementation Method 2
selective removal of a high Ge concentration sacrificial layer
Data Source
AI summary
A semiconductor device includes a substrate, a first shallow trench isolation (STI) liner disposed above and in contact with the substrate, a bottom dielectric isolation (BDI) region disposed above the substate and in contact with the STI liner, a device channel disposed above the BDI region, and a gate stack disposed above and in contact with the device channel.