Junctionless FET Metal-Interlayer-Semiconductor Structure
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Solution Overview
Problem
Junctionless field-effect transistors face challenges with high Schottky barrier at the source/drain region, leading to current leakage and limited operation in enhancement mode due to precision processing difficulties and increased power consumption.
Innovation Solution
A metal-interlayer-semiconductor structure is introduced, with a dielectric layer inserted between the semiconductor and source/drain electrodes, using low-temperature processes to reduce contact resistance and alleviate Fermi-level pinning, allowing the transistor to operate in enhancement mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal-semiconductor structure is used at the source/drain region, then contact resistance is reduced, but current leakage increases due to high Schottky barrier
Solution Approach 1:
A dielectric layer is introduced as an intermediary between the metal source/drain electrode and the semiconductor layer. This dielectric layer acts as a mediator that reduces the Schottky barrier height at the metal-semiconductor interface, thereby reducing current leakage while maintaining low contact resistance through the metal-interlayer-semiconductor structure.
Solution Approach 2:
The patent employs a composite structure consisting of metal, dielectric, and semiconductor layers. This composite material approach creates a metal-interlayer-semiconductor structure where the dielectric component modifies the electrical properties at the interface, enabling simultaneous achievement of low contact resistance and reduced current leakage by optimizing the combined properties of the composite structure.
2Manufacturing precision
If conventional MOSFET or FinFET structures are used, then manufacturing precision is maintained, but switching characteristics degrade due to scaling limits
Solution Approach 1:
The patent transitions from conventional MOSFET/FinFET structures to a junctionless field-effect transistor structure with metal source/drain electrodes and a dielectric interlayer. This parameter change in the device architecture enables improved switching characteristics by eliminating the need for precise source/drain doping while maintaining manufacturability through standard fabrication processes.
3Ease of operation
If junctionless field-effect transistor structure is adopted, then switching characteristics are improved, but power consumption increases due to high Schottky barrier
Solution Approach 1:
The dielectric layer serves as an intermediary that reduces the Schottky barrier at the metal-semiconductor interface in the junctionless field-effect transistor. By lowering the barrier height, carrier injection efficiency is improved, reducing the power required for operation while preserving the enhanced switching characteristics of the junctionless structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces current leakage and achieves low contact resistance, enabling the junctionless field-effect transistor to operate in enhancement mode while minimizing power consumption.
Implementation Method 1
current leakage caused by a high Schottky barrier at the source/drain
Implementation Method 2
alleviate Fermi-level pinning
Implementation Method 3
A junctionless field-effect transistor can adjust the size of the depletion layer region of the channel through the gate work function
Data Source
AI summary
A semiconductor component is disclosed. The semiconductor component can include: a semiconductor layer injected with a same type of dopant; a gate electrode formed above the semiconductor layer with a gate insulation film positioned in-between; a dielectric layer formed on the semiconductor layer at both sides of the gate electrode; and source/drain electrodes each formed on the dielectric layer.