Nanosheet Transistor Self-Aligned Dielectric Pillar
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Solution Overview
Problem
The increasing parasitic capacitance in nanosheet transistor architectures due to trench silicide-to-gate capacitance limits the scaling of field-effect transistors, leading to slower circuit speeds and higher power consumption.
Innovation Solution
A self-aligned dielectric pillar is formed between the source/drain regions of nanosheet stacks, serving as an etch stop for the source/drain trench contact trench patterning, thereby reducing the vertical depth of the trench silicide and minimizing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If trench silicide is formed in deep contact trenches to connect source/drain regions, then electrical connectivity is improved, but parasitic capacitance between trench silicide and gate increases
Solution Approach 1:
A dielectric pillar is introduced as an intermediary structure between the trench silicide and the gate. This dielectric material acts as a mediator that electrically isolates the trench silicide from the gate, thereby reducing parasitic capacitance while allowing the trench silicide to maintain its electrical connectivity function with the source/drain regions
Solution Approach 2:
The solution moves from a two-dimensional planar contact structure to a three-dimensional structure by forming vertical dielectric pillars. This dimensional change allows the trench silicide to extend deeper into the contact trench while the dielectric pillar provides vertical isolation, reducing capacitive coupling between the trench silicide and gate that would otherwise increase with trench depth
2Quantity of substance
If transistor scaling is pursued to increase device density, then device density is improved, but parasitic capacitance effects become more significant
Solution Approach 1:
The gate structure is segmented into multiple nanosheets stacked vertically, with dielectric pillars positioned between adjacent nanosheets. This segmentation creates isolated capacitive regions, preventing the formation of a large continuous parasitic capacitance that would limit scaling. Each nanosheet-gate interface has reduced parasitic capacitance compared to a single large gate structure
Solution Approach 2:
Dielectric pillars are positioned between the trench silicide and gate structure to act as intermediary isolation elements. This mediation reduces the direct capacitive coupling that would otherwise scale with device density, allowing higher device density to be achieved without proportionally increasing parasitic capacitance effects
3Object-generated harmful factors
If self-aligned dielectric pillar is formed to reduce parasitic capacitance, then parasitic capacitance is reduced, but manufacturing process complexity increases
Solution Approach 1:
The dielectric pillar is formed preliminarily before the trench silicide deposition step. By pre-forming the dielectric isolation structure, the subsequent trench silicide formation becomes simpler as it only requires filling the remaining contact trench space. This preliminary action prevents the need for complex post-processing steps to add isolation after silicide formation
Solution Approach 2:
The formation of the dielectric pillar is merged with the existing contact trench patterning process. The same etch process used to define the contact trench location also defines the dielectric pillar position, and the dielectric material deposition is combined with other dielectric layer formation steps in the process flow, reducing overall process complexity despite the additional structural element
Data Source
AI summary
Embodiments of the present invention are directed to a semiconductor structure and a method for forming a semiconductor structure having a self-aligned dielectric pillar for reducing trench silicide-to-gate parasitic capacitance. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. A dielectric pillar is positioned adjacent to the nanosheet stack and on a shallow trench isolation region of the substrate. The nanosheet stack is recessed to expose a surface of the shallow trench isolation region and a source or drain (S/D) region is formed on the exposed surface of the shallow trench isolation region. A contact trench is formed that exposes a surface of the S/D region and a surface of the dielectric pillar.