Nanosheet Nanowire CFET Structure for Vertical Stacking Stability
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Solution Overview
Problem
Current complementary field-effect transistor (CFET) structures face mechanical instability and challenges in patterning different work function metals for vertically stacked n-type and p-type field-effect transistors, particularly at advanced technology nodes like 5 nm and beyond.
Innovation Solution
A semiconductor structure comprising a stack of nanosheet layers and nanowires with vertically aligned gates and source/drain regions, where the nanosheet stacks alternate between silicon and silicon-germanium layers, allowing for mechanical stability and easy patterning of distinct work function metals for each transistor type.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If gate-all-around technology is used for stacking PFET and NFET transistors, then device scaling is improved, but mechanical stability deteriorates
Solution Approach 1:
The channel region is segmented into multiple thin nanosheet layers stacked vertically, with each layer providing mechanical support. This segmentation allows the device to achieve smaller lateral dimensions while maintaining structural integrity through the distributed support of multiple layers.
Solution Approach 2:
The device employs composite material structure combining silicon nanosheets for the channel with surrounding gate materials and dielectric layers. This composite approach provides both the electrical functionality and mechanical reinforcement needed for stable operation at scaled dimensions.
2Productivity
If vertically stacked CFET structure is implemented, then device density is improved, but patterning of different work function metals becomes more difficult
Solution Approach 1:
The gate structure is segmented into laterally separated regions with different work function metals, allowing independent patterning of each metal type. This segmentation enables the manufacturing process to deposit and pattern different metals in separate steps rather than requiring complex simultaneous patterning.
Solution Approach 2:
The work function metals are deposited and patterned before the final gate closure step. This preliminary action allows each metal region to be precisely patterned while the structure is still accessible, avoiding the difficulty of patterning through already-closed gate structures.
Data Source
AI summary
A semiconductor structure includes a first field-effect transistor disposed on a substrate. The first field-effect transistor includes a stack of nanosheet layers, a first gate, and a first source/drain region. The semiconductor structure further includes a second field-effect transistor vertically stacked above the first field-effect transistor. The second field-effect transistor includes a plurality of nanowires, a second gate, and a second source/drain region. The first gate and the second gate are vertically aligned. The first source/drain region and the second source/drain region are vertically aligned.