Air Gap Regions Below Source/Drain in 3D Semiconductor Devices
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Solution Overview
Problem
The increasing demand for improved performance, faster operating speeds, and expanded functionality in semiconductor devices necessitates the development of three-dimensional (3D) semiconductor structures to overcome the limitations of planar metal oxide semiconductor (MOS) field effect transistors (FETs).
Innovation Solution
The semiconductor device incorporates a substrate with an active region, a gate structure intersecting the active region, channel layers surrounded by the gate structure, source/drain regions connected to the channel layers, and air gap regions between the source/drain regions and the active region. The semiconductor layers are alternately disposed with the air gap regions to define them, with the lower ends of the source/drain regions located at a level lower than the uppermost air gap region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar MOS FET structure is used, then manufacturing is simpler, but operating characteristics deteriorate due to size limitations
Solution Approach 1:
The patent transitions from a planar 2D structure to a 3D vertical structure by stacking multiple channel layers (first, second, third channel layers) in the vertical direction. This dimensional change allows the device to achieve better operating characteristics through increased effective channel area and improved current drive capability while maintaining manufacturing feasibility through extended epitaxial growth processes.
2Loss of energy
If source/drain regions are enlarged to decrease resistance, then conductivity improves, but leakage current increases
Solution Approach 1:
The patent divides the source/drain structure into multiple discrete regions: first source/drain regions connected to the first channel layer, second source/drain regions connected to the second channel layer, and third source/drain regions connected to the third channel layer. This segmentation allows each source/drain region to be optimized independently, achieving low resistance through multiple contact points while preventing leakage current by isolating doped regions through undoped semiconductor layers between them.
Solution Approach 2:
The patent introduces undoped semiconductor layers as intermediary regions between the doped source/drain regions. These undoped layers act as barriers that prevent carrier diffusion and leakage current between adjacent source/drain regions, while the overall multi-layer structure maintains low resistance through parallel current paths. The gate structure also serves as an intermediary control element that modulates current flow between source and drain.
3Productivity
If integration density is increased, then functionality expands, but stress on channel structures increases
Solution Approach 1:
The patent achieves high integration density by stacking multiple channel layers vertically rather than expanding laterally. This vertical stacking increases the effective channel area and current capacity without increasing the planar footprint, thereby maintaining mechanical strength and reducing stress on individual channel structures while achieving enhanced functionality and productivity.
Data Source
AI summary
A semiconductor device includes a substrate having an active region extending in a first direction; a gate structure disposed on the substrate, intersecting the active region, and extending in a second direction; channel layers disposed on the active region to be spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, and to be surrounded by the gate structure; source/drain regions disposed on both sides of the gate structure and connected to the channel layers; air gap regions located between the source/drain regions and the active region and spaced apart from each other in the third direction; and semiconductor layers alternately disposed with the air gap regions in the third direction and defining the air gap regions, wherein lower ends of the source/drain regions are located on a level lower than an uppermost air gap region.