Integrating Thick and Thin Nanosheet Transistors on Single Chip
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Solution Overview
Problem
The integration of thick and thin oxide nanosheet metal oxide semiconductor field effect transistors (MOSFETs) on a single chip is limited by the need for tight device-device spacing, which restricts device scaling and compatibility between high voltage and logic devices due to differences in gate dielectric thickness.
Innovation Solution
A method is developed to integrate thick oxide nanosheet transistors with a single layer channel and thin oxide nanosheet transistors with multiple layers of channels on a single chip, using alternating layers of materials and selective etching to form spacers and gate oxides, allowing for compatibility between high voltage and logic applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If tight device-device spacing is used to reduce device size, then device scaling is improved, but device complexity increases and manufacturing precision requirements worsen
Solution Approach 1:
The patent divides the nanosheet stack into multiple discrete nanosheets separated by gaps. These gaps are selectively filled with dielectric material to form spacers, creating distinct active and inactive regions. This segmentation allows precise control over device spacing and enables the integration of multiple device types on a single chip without compromising manufacturing precision.
Solution Approach 2:
The patent implements local quality by having different nanosheets within the same stack serve different functions. Some nanosheets are converted to thick-oxide devices for high voltage operation, while others remain as thin-oxide devices for logic applications. This local differentiation allows simultaneous optimization of different device regions for their specific requirements while maintaining tight overall device spacing.
2Reliability
If thicker gate dielectric is used for high voltage operation, then voltage operation capability is improved, but device scaling capability worsens
Solution Approach 1:
The patent segments the gate dielectric thickness across different nanosheets within the same stack. Each nanosheet can have independently tailored dielectric thickness to match its voltage requirements. This allows high voltage devices to use thicker dielectrics while logic devices use thinner dielectrics, enabling both to coexist on the same chip without compromising device scaling.
Solution Approach 2:
The patent applies local quality by varying the gate dielectric thickness locally across different nanosheets. Thick oxide is formed on nanosheets designated for high voltage operation, while thin oxide is formed on nanosheets for logic applications. This local differentiation resolves the contradiction by allowing each region to have the dielectric thickness optimized for its specific voltage requirements.
3Power
If smaller spacing between nanosheets is used to realize capacitance benefits, then electrical performance is improved, but device complexity increases
Solution Approach 1:
The patent uses segmentation to create gaps between specific nanosheets and selectively fills these gaps with dielectric material to form spacers. This approach maintains small effective spacing for capacitance benefits while using the spacer structure to simplify the overall device architecture by clearly defining active and inactive regions, thereby reducing device complexity.
Data Source
AI summary
A method is presented for integrating a first nanosheet transistor and a second nanosheet transistor on a chip. The method includes constructing the first nanosheet transistor by forming a first nanosheet stack including alternating layers of a first material and a second material over a substrate, forming a dummy gate and first spacers over the first nanosheet stack, selectively etching the alternating layers of the first material to define gaps between the alternating layers of the second material, filling the gaps with second spacers, removing the dummy gate, removing a portion of the first nanosheet stack including layers of the first and second materials, and selectively removing remaining layers of the second material such that a single layer of the first material remains intact to define a single nanosheet channel. The method includes constructing the second nanosheet transistor by forming a second nanosheet stack having multiple layers of nanosheet channels.