Multi-Gate Semiconductor Device for SRAM Leakage Reduction
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Solution Overview
Problem
Existing gate-all-around (GAA) FET devices have limitations due to incomplete control over the channel region, particularly the bottom side, leading to suboptimal performance in terms of short-channel effects and leakage current in memory devices like SRAM cells.
Innovation Solution
A method for forming multi-gate semiconductor structures with a fin structure that eliminates the need for a fin-cut operation, allowing for the formation of GAA devices without polysilicon over diffusion edges (PODE), thereby ensuring complete control over the channel region and reducing leakage current by using sacrificial gates, spacers, and epitaxial structures to create a metal gate configuration that surrounds the fin, ensuring all sides of the channel are controlled.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a FinFET gate structure is used where the gate electrode is positioned adjacent to three side surfaces of the channel region, then the gate structure surrounds the fin on three sides providing good control, but the bottom part of the channel region is positioned far away from the gate electrode resulting in incomplete control and increased leakage current
Solution Approach 1:
The gate electrode is extended into the third dimension to completely surround the channel region, transitioning from a planar three-side configuration to a four-side all-around configuration. This dimensional extension ensures that the gate electrode is positioned close to all surfaces of the channel region including the bottom part, achieving complete depletion and reducing leakage current through enhanced electrostatic control.
Solution Approach 2:
The gate structure employs a composite configuration where the gate electrode wraps around the channel region from multiple directions, creating a gate-all-around architecture. This composite spatial arrangement allows the gate to exert control over all surfaces of the channel, eliminating the harmful effect of incomplete control at the bottom surface and significantly reducing short-channel effects and leakage current.
2Reliability
If existing GAA FET fabrication methods are used, then GAA devices can be formed, but fin-cut operations are required and polysilicon over diffusion edges (PODE) are formed leading to increased complexity and manufacturing costs
Solution Approach 1:
The fin-cut operation step is completely removed from the fabrication process. The method achieves GAA FET formation without requiring fin-cut operations, thereby eliminating the associated complexity and manufacturing costs while maintaining complete gate control over the channel region. The gate electrode is formed to surround the channel in a manner that does not necessitate fin removal or cutting steps.
Solution Approach 2:
Instead of forming the gate structure and then performing fin-cut operations to achieve complete control, the method inverts the approach by designing the gate electrode configuration from the outset to completely surround the channel region without requiring any fin-cut steps. This reversal of the conventional sequence eliminates PODE formation and simplifies the overall fabrication process while achieving the same or better gate control.
Data Source
AI summary
A memory device includes a first SRAM cell, a second SRAM cell, a first inter transistor and a second inter transistor. The first SRAM cell includes two first pull-up transistors, two first pull-down transistors, and two first pass-gate transistors. The second SRAM cell includes two second pull-up transistors, two second pull-down transistors, and two second pass-gate transistors. The first inter transistor and the second inter transistor are electrically connected to the first SRAM cell and the second SRAM cell.