Gate Structure Capping Layer Segmentation for Nano-FET Yield
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in maintaining the integrity and yield of nanostructure field-effect transistors (nano-FETs) during manufacturing, particularly in avoiding merging or seaming of capping layers during anneal processes, which can damage underlying features and reduce manufacturing yield.
Innovation Solution
A capping layer made of sacrificial material with good oxidation resistance and conformality, deposited using atomic layer deposition, protects the work function tuning layer during annealing and is easily removable to prevent damage, allowing for precise tuning of work functions and avoiding merging or seaming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capping layer is deposited to protect the work function tuning layer during annealing, then the work function tuning effectiveness is improved, but the capping layer may merge or seam during annealing which damages underlying features and reduces manufacturing yield
Solution Approach 1:
The capping layer is segmented into multiple discrete segments rather than a continuous layer. This segmentation prevents merging and seaming during annealing processes, as each segment remains spatially separated. The segments can be formed through patterned deposition techniques such as shadow mask deposition or selective area deposition, allowing the capping layer to fulfill its protective function while avoiding the defects associated with continuous layer formation.
Solution Approach 2:
The capping layer segments are deposited beforehand before the annealing process that forms metal silicide regions. This preliminary action allows the capping layer to be in place to prevent oxidation of the work function tuning layer during subsequent processing steps, including the annealing that creates the silicide regions. The segments are positioned and formed with appropriate spacing to prevent merging during thermal processing.
2Manufacturing precision
If the capping layer thickness is reduced to avoid merging, then the manufacturing yield is improved, but the protection effectiveness during annealing is reduced
Solution Approach 1:
Rather than reducing the thickness of a continuous capping layer, the invention segments the capping layer into multiple discrete regions. This segmentation approach allows each segment to maintain adequate thickness for oxidation protection during annealing, while the spatial separation between segments prevents merging and seaming defects. The segment geometry and spacing are optimized to provide sufficient protective coverage while avoiding defect formation.
Solution Approach 2:
The capping layer structure implements local quality by having different spatial distributions - each local segment maintains sufficient thickness for protection, while the global structure uses spaced segments to prevent merging. The segment dimensions, spacing, and coverage distribution are locally optimized to balance protection effectiveness with defect prevention, allowing thick enough segments for protection while spaced far enough apart to avoid merging during thermal processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the manufacturing yield of nano-FETs by preventing damage to underlying features and allowing for effective work function tuning, improving the performance and reliability of the devices.
Implementation Method 1
A capping layer 116 made of sacrificial material with good oxidation resistance and conformality, deposited using atomic layer deposition, protects the work function tuning layer during annealing
Implementation Method 2
deposited using atomic layer deposition
Implementation Method 3
performing an anneal process while the capping layer covers the work function tuning layer, the anneal process driving the first work function tuning element from the work function tuning layer into the gate dielectric layer
Data Source
AI summary
In an embodiment, a method includes: forming a gate dielectric layer on a channel region of a semiconductor feature; depositing a work function tuning layer on the gate dielectric layer, the work function tuning layer including a first work function tuning element; depositing a capping layer on the work function tuning layer with atomic layer deposition, the capping layer formed of an oxide or a nitride; performing an anneal process while the capping layer covers the work function tuning layer, the anneal process driving the first work function tuning element from the work function tuning layer into the gate dielectric layer; removing the capping layer to expose the work function tuning layer; and depositing a fill layer on the work function tuning layer.