3D Semiconductor Assembly With Well Alignment for Bonding Quality
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Solution Overview
Problem
Existing three-dimensional integrated circuits (3DICs) face challenges in reducing bonding failure risk during semiconductor assembly, particularly due to issues with bonding quality and surface area degradation from chemical-mechanical planarization processes.
Innovation Solution
The semiconductor assembly involves stacking semiconductor elements with wells of different doping types, ensuring a sufficient bonding surface area by aligning wells vertically and using hybrid bonding techniques without chemical-mechanical planarization, thereby enhancing bonding quality and reducing failure risk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If chemical-mechanical planarization is used to prepare bonding surfaces, then surface flatness is improved, but bonding surface area is reduced due to rounding corners and sloping edges
Solution Approach 1:
The patent removes the chemical-mechanical planarization step from the bonding preparation process. By eliminating this process, the harmful rounding and sloping effects are avoided, preserving the full bonding surface area while achieving sufficient flatness through alternative means (direct polishing or controlled etching)
Solution Approach 2:
Instead of using chemical-mechanical planarization to achieve flatness (conventional approach), the patent inverts the approach by using direct mechanical polishing or controlled anisotropic etching to achieve the desired surface preparation. This reversal avoids the harmful side effects of C-M-P while maintaining surface quality for bonding
2Device complexity
If conventional bonding processes are used without well alignment, then manufacturing complexity is reduced, but bonding quality and reliability deteriorate
Solution Approach 1:
The patent performs well alignment and positioning actions before the actual bonding process. By pre-aligning the p-type and n-type wells between substrates and ensuring proper conductive via positioning, the bonding quality is enhanced without requiring complex post-bonding adjustments or rework
Solution Approach 2:
The patent replaces complex mechanical alignment systems with a design-based alignment approach. By incorporating alignment marks, keyed features, or pre-defined well patterns that guide the bonding process, the need for sophisticated mechanical positioning systems is reduced while maintaining high bonding quality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves bonding quality and reduces the risk of failure by maintaining a larger bonding surface area and preventing rounding corners or sloping edges, ensuring robust electrical connections between stacked semiconductor elements.
Implementation Method 1
3DICs use bonding technology to stack multiple semiconductor chips
Implementation Method 2
a first well in the first substrate and having a first doping type, a second well in the second substrate and having a second doping type
Data Source
AI summary
A semiconductor assembly and a method for manufacturing the same are provided. The semiconductor assembly includes a first substrate, a first well in the first substrate and having a first doping type, a second substrate, a second well in the second substrate and having a second doping type, a first dielectric layer between the first substrate and the second substrate, and a second dielectric layer between the first substrate and the second substrate. The first doping type is different from the second doping type. The second dielectric layer is bonded to the first dielectric layer. The first well overlaps with the second well in a vertical direction.