3D Shared Data Bus Using Stacked IC Interconnect Layers
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Solution Overview
Problem
As semiconductor technology advances, the limitations of Moore's Law have been reached, making it challenging to further increase the number of transistors on an IC chip, necessitating innovative approaches to enhance semiconductor substrate capacity.
Innovation Solution
A three-dimensional (3D) circuit is formed by stacking two or more integrated circuit (IC) dies to share interconnect layers for power, clock, and data-bus signals, utilizing direct bonding techniques like DBI to establish a large number of direct connections between the top interconnect layers, allowing for orthogonal wiring directions that reduce capacitive load and increase connection density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more interconnect layers are added to increase transistor capacity, then the number of transistors that can be defined increases, but the chip area and manufacturing complexity increase
Solution Approach 1:
The patent merges interconnect layers from multiple IC dies by stacking them in a 3D configuration. Specifically, interconnect layers from different dies are bonded together to form shared interconnect structures that serve multiple functional blocks across dies, thereby reducing the total number of interconnect layers needed while increasing transistor capacity.
Solution Approach 2:
The patent transitions from a 2D planar arrangement of interconnect layers to a 3D stacked configuration. By stacking IC dies vertically and bonding their interconnect layers, the system adds a third dimension to interconnect routing, enabling shorter signal paths and reduced capacitive load without increasing chip area.
2Area of stationary object
If interconnect layers are shared between stacked IC dies, then chip space is optimized and connection density increases, but the difficulty of detecting and measuring signal integrity increases
Solution Approach 1:
The patent segments the interconnect structure into distinct bonded interfaces between stacked dies. Each interface can be independently characterized and tested, allowing signal integrity to be measured at specific bonding points rather than across the entire complex interconnect network, thereby reducing measurement difficulty.
3Productivity
If direct bonding techniques are used to establish connections between interconnect layers, then connection density and signal routing efficiency improve, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary alignment features such as alignment marks and guide structures fabricated on the IC dies before bonding. These features enable precise registration of interconnect layers during the stacking process, reducing the manufacturing precision requirements for the actual bonding operation while maintaining high connection density.
Data Source
AI summary
Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.