3D SoC Atomic Handling Across Disaggregated CXL Dies
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Solution Overview
Problem
Conventional systems fail to address the handling of atomic transactions in a disaggregated 3D-structured System on a Chip (SoC) architecture, which is a new architectural approach.
Innovation Solution
A disaggregated 3D-structured SoC architecture is designed with a package substrate interfaced with a bottom level cache die and additional system die, utilizing Compute Express Link (CXL) interconnects to handle atomic operations, including system and local memory transactions through an atomic handler that routes and performs atomic operations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a disaggregated 3D-structured SoC architecture is implemented, then modular scalability and adaptability are improved, but device complexity increases due to multiple dies and interconnect requirements
Solution Approach 1:
The SoC is divided into multiple independent dies (compute die, memory die, I/O die) that can be manufactured separately and then interconnected. This segmentation enables modular scalability where individual dies can be upgraded or replaced independently, directly resolving the contradiction by allowing adaptability improvement while managing complexity through standardized interconnect interfaces.
Solution Approach 2:
Standardized interconnect interfaces (such as CXL protocols) are introduced as intermediaries between different dies. These intermediaries provide a uniform communication layer that simplifies the integration complexity while enabling flexible modular configurations, thus resolving the contradiction between scalability and complexity.
2Reliability
If atomic operations are handled through a dedicated atomic handler in the disaggregated architecture, then transaction handling reliability is improved, but device complexity increases due to additional routing logic
Solution Approach 1:
The atomic operation handling logic is extracted into a dedicated atomic handler component within the interconnect fabric. This separation allows atomic transactions to be processed through specialized logic while regular transactions follow standard routing paths, improving reliability without significantly increasing overall system complexity through functional decomposition.
Solution Approach 2:
The atomic handler is designed as a multi-functional component that can handle various types of atomic operations (read-modify-write, compare-and-swap, etc.) and different operand sizes through a unified interface. This universality reduces the need for multiple specialized handlers, thereby limiting the increase in device complexity while maintaining high reliability.
3Quantity of substance
If multiple memory dies are interfaced through CXL interconnects, then memory capacity and bandwidth are improved, but loss of time increases due to additional interconnect hops for atomic operations
Solution Approach 1:
The system performs preliminary actions by caching data that is likely to be involved in atomic operations into local caches on the compute die or in intermediate buffer memory. This preliminary caching reduces the frequency of long-distance interconnect hops for atomic operations, thereby maintaining high memory capacity while reducing the time penalty associated with disaggregated memory access.
Data Source
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AI summary
In a further embodiment, A system on a chip integrated circuit, SoC, including an active base die including a first cache memory and first and second die interconnects; a first die (406) mounted on the active base die, the first die including an interconnect fabric, and a third die interconnect to couple to the first die interconnect; and a second die mounted on the active base die, the second die comprising a fourth die interconnect to couple with the second die interconnect and including an array of graphics processing elements coupled to the first cache memory of the active base die via the fourth die interconnect.