Memory Architecture Accessing/Allocation TRIZ Cases
- MMU Crossbar Mapping for Secure Multi-Tenant Memory Protection
A crossbar-based N+D MMU mapping cuts mapping growth and avoids runtime reconfiguration that can expose multi-tenant memory to attacks.
- Memory Controller Scheduling with Region-Specific Timing Profiles
Region-specific timing profiles let a memory controller avoid worst-case scheduling, cutting latency and improving bandwidth.
- Mid-Tier Cache Revalidation Using Metadata-Only Retrieval
Mid-tier servers cache freshness metadata instead of full multimedia assets to cut revalidation traffic, storage use, and origin load.
- Wide LAG and ECMP Control Using Per-Flow Queuing
Per-flow queues and acknowledgment-based flow channels speed wide LAG and ECMP congestion control while preventing buffer overflow.
- Cache Read Queue Prefetching for Memory Transfer Latency
Dual read queues pre-send memory requests and stage data in a controller buffer to cut cache wait time and handle read-after-write delays.
- Secure Enclave Data Processing for Privacy-Preserving Recommendations
Trusted enclaves isolate encrypted partner data so recommendations can be generated without exposing raw consumer information or overloading external systems.
- Cache-Coherent Memory Booting During Server Memory Training
Pre-allocated cache-coherent memory lets servers boot and run workloads while local memory trains, cutting reboot downtime.
- Cache Directory Conflict Monitoring for Page Mapping Rebalancing
Eviction conflict data from page-level cache directories guides OS or hypervisor page remapping to cut latency and improve performance.
- SSD Die Partitioning by Spare Blocks for Wear-Balanced Workloads
By grouping SSD dies by spare block count, write-heavy and read-heavy workloads can be separated to balance wear and extend drive endurance.
- Memory Encryption Verification Using Physical Access Measurements
Physical measurements during memory access reveal whether transparent encryption is active, helping detect insecure processor or VM configurations.
- 3D SoC Atomic Handling Across Disaggregated CXL Dies
A dedicated atomic handler routes CXL memory transactions across disaggregated 3D SoC dies to improve atomic operation throughput and scalability.
- SSD NAND Stream Migration for Burst Write Fragmentation
Adaptive migration across high- and low-performance NAND regions preserves data order during burst writes and reduces SSD fragmentation.
- Inline Computational Storage for Reduced Data Transfer Latency
Processing data inside the storage unit cuts transfer latency, reduces host processor load, and returns results from a single command.