Cache-Coherent Memory Booting During Server Memory Training

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Solution Overview

Problem

Server reboots in data centers, necessitated by critical firmware updates and disaster recovery, result in significant downtime due to memory retraining, leading to cumulative compute time losses and inefficiencies as memory training is limited by architecture and protocols.

Innovation Solution

Implementing cache-coherent interconnect memory with pre-allocated regions in a shared memory pool, allowing BIOS to boot the OS from pre-allocated memory while training and initializing local memory in the background, ensuring seamless workload execution without interruptions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If server memory is retrained during reboot, then memory reliability is improved, but system downtime increases

Engineering Contradiction:
Improvememory reliabilityVSAvoidsystem downtime
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent pre-allocates memory regions from a pooled memory resource before the compute node needs to boot. This preliminary allocation allows the memory to be ready for use without requiring time-consuming retraining operations during the reboot process, thus resolving the contradiction between ensuring memory reliability and minimizing system downtime.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a pooled memory resource as an intermediary between the compute node and the memory training process. By using this intermediate memory pool, the system can perform memory operations without directly impacting the compute node's operational memory, allowing reliable memory operations to proceed while minimizing interruption to the compute node.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If memory retraining is performed during server reboot, then memory operation reliability is improved, but compute time is lost

Engineering Contradiction:
Improvememory operation reliabilityVSAvoidcompute time
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

Memory regions are pre-allocated and prepared in advance before the compute node requires them for workload execution. This preliminary preparation ensures that when the compute node needs memory, it is already ready for reliable operation, eliminating the need to perform time-consuming training operations during the compute cycle and thus preserving productivity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent enables continuous workload execution by using a pooled memory resource that can be allocated without interrupting the compute node's operational flow. The memory pool serves as a continuous resource that can be accessed immediately, maintaining uninterrupted compute time while still ensuring reliable memory operations through the pooling mechanism.

Inventive Principle:
Principle #20Continuity of useful action

3Reliability

If local memory is trained and initialized, then memory reliability is ensured, but workload execution is interrupted

Engineering Contradiction:
Improvememory reliabilityVSAvoidworkload execution continuity
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

The patent segments memory into a pooled memory resource and local memory. The pooled memory can be allocated and prepared independently without affecting the local memory that is actively being used for workload execution. This segmentation allows memory reliability to be ensured through proper allocation and initialization of the pool while keeping workload execution on local memory uninterrupted.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The pooled memory resource acts as an intermediary that handles memory allocation and initialization operations separately from the local memory used for active workloads. This intermediary structure allows the system to perform necessary memory preparation for reliability without directly interrupting the continuous operation of local memory-based workloads.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP4685634A1Server fast boot using cache-coherent interconnect memory
Publication Date: 2026.01.28 MICROSOFT TECHNOLOGY LICENSING LLC
  • EP4685634A1 patent drawingFigure 1
  • EP4685634A1 patent drawingFigure 2A
  • EP4685634A1 patent drawingFigure 2B

AI summary

Systems and methods are provided for implementing server fast boot using cache-coherent interconnect memory. A cache-coherent interconnect node partitions a memory pool and pre-allocates a memory region of the memory pool to each compute node of a plurality of compute nodes. A basic input/output system ("BIOS") of a compute node maps a local memory of the compute node to a memory region that has been pre-allocated to the compute node. The BIOS boots an operating system ("OS") of the compute node in the memory region. Concurrent with the OS executing workloads using the memory region, the BIOS trains and initializes the local memory, after completion of which the BIOS notifies the OS that the local memory is ready. The OS migrates contents from the memory region to the local memory, and subsequently executes the workload from the local memory or a combination of the local memory and the memory region.