3D SRAM Transistor Layout for Higher Integration Density
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Solution Overview
Problem
The integration and size of static random access memory (SRAM) cells are limited due to the arrangement of six transistors, making it difficult to improve the degree of integration.
Innovation Solution
The transistors in the SRAM cell are arranged such that the first transistor group at the first level and the second transistor group at the second level overlap each other vertically, with specific conductivity types and electrical connections, allowing for a more efficient use of space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If six transistors are arranged in a single SRAM cell using conventional layout, then the SRAM cell can be configured with standard circuit topology, but the degree of integration is limited and device size is large
Solution Approach 1:
The patent applies three-dimensional stacking by dividing transistors into first and second levels that overlap vertically. The first transistor group (including first pass transistor and first pull-up transistor) is disposed at a first level, while the second transistor group (including second pass transistor and second pull-up transistor) is disposed at a second level above the first level. This vertical arrangement in the third dimension reduces the planar area occupied by each SRAM cell while maintaining all necessary circuit functions, thereby improving integration density.
2Area of moving object
If transistors are arranged in overlapping vertical levels, then the SRAM cell size is reduced and integration is improved, but the device structure becomes more complex
Solution Approach 1:
The patent segments the six-transistor SRAM cell into two distinct groups: a first transistor group at a first level and a second transistor group at a second level. Each group contains specific transistors (first pass transistor with first pull-up transistor, and second pass transistor with second pull-up transistor). This segmentation allows for systematic vertical stacking while maintaining clear functional separation, making the complex structure more manageable and manufacturable.
Solution Approach 2:
The patent merges the first and second levels vertically by disposing transistor groups at different heights that overlap in the planar view. The first level and second level are combined in the vertical dimension, allowing transistors from both levels to share the same footprint area. This merging approach maximizes space utilization and reduces the overall cell area while maintaining electrical isolation between levels through appropriate insulating structures.
Data Source
AI summary
A semiconductor device may include: a first lower active pattern extending in a first direction and including a first lower channel pattern; a second lower active pattern extending in the first direction; a first upper active pattern extending in the first direction; a second upper active pattern extending in the first direction; a first gate structure extending in the second direction; a second gate structure extending in the second direction; a first lower source/drain pattern disposed on one side of the first lower channel pattern; a first upper source/drain pattern disposed on one side of the first upper channel pattern; a second lower source/drain pattern disposed on one side of the second lower channel pattern; and a second upper source/drain pattern disposed on one side of the second upper channel pattern.