3D Stack Memory Device with Tunnel FETs
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Solution Overview
Problem
Current memory devices face limitations in integration density, switching performance, and power consumption, particularly in densely packed configurations, necessitating the development of next-generation memory devices with high capacity, speed, and low power consumption.
Innovation Solution
A 3D stack memory device is designed with a semiconductor substrate, stacked active patterns, tunnel field effect transistors (FETs), and resistive device layers, incorporating a source and drain with different conductivity types, and a common source line connected to resistive device layers, enhancing integration density and switching performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are integrated in a narrow area to improve integration density, then integration density is improved, but switching performance deteriorates
Solution Approach 1:
The patent transitions from planar 2D memory cell arrangement to a 3D vertical stack configuration. Multiple active regions are stacked vertically over the semiconductor substrate, allowing memory cells to be arranged in three dimensions rather than confined to a single plane. This dimensional change enables higher integration density while maintaining sufficient lateral spacing to preserve switching performance of individual cells.
Solution Approach 2:
The memory device is segmented into multiple discrete active regions stacked vertically, with each active region containing its own switching device and resistive device. The stack includes alternating active regions and insulation layers, creating modular units that can be independently controlled. This segmentation allows each memory cell to maintain its switching performance while achieving high overall integration density through vertical stacking.
2Quantity of substance
If multiple memory cells are integrated in a limited area, then integration density is improved, but power consumption increases
Solution Approach 1:
The source line is designed as a common shared resource that serves all resistive devices in the stack, rather than providing separate source lines to each device. This multi-functional approach reduces the total number of interconnect lines required, thereby reducing overall power consumption while maintaining high integration density. The bit lines similarly serve multiple active regions vertically.
Solution Approach 2:
By stacking memory cells vertically, the patent reduces the lateral area required per memory cell, allowing more cells to be integrated in a limited footprint without proportionally increasing power consumption. The vertical arrangement enables shared interconnect structures that reduce overall device power requirements compared to planar scaling.
3Device complexity
If conventional switching devices are used, then device complexity is low, but switching performance at low voltage is insufficient
Solution Approach 1:
The patent employs tunnel field effect transistors (TFETs) that utilize quantum mechanical tunneling effects to achieve sub-threshold swing less than 60 mV/decade, enabling effective switching at voltages below conventional thresholds. This parameter change in the switching mechanism allows high-speed operation at low voltages, improving switching performance without significantly increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3D stack memory device achieves improved integration density and switching performance, particularly at low voltages, by utilizing tunnel FETs and resistive device layers, enabling efficient data storage and retrieval in a compact, low-power consumption configuration.
Implementation Method 1
tunnel field effect transistor (FET)
Data Source
AI summary
A 3-dimensional stack memory device includes a semiconductor substrate, a stacked active pattern configured so that a plurality of stripe shape active regions and insulation layers are stacked alternatively over the semiconductor substrate, a gate electrode formed in the stacked active pattern, a source and drain formed at both sides of the gate electrode in each of the plurality of active regions, a bit line formed on one side of the drain to be connected to the drain, a resistive device layer formed on one side of the source to be connected to the source, and a source line connected to the resistive device layer. The source is configured of an impurity region having a first conductivity type, and the drain is configured of an impurity region having a second conductivity type different from the first conductivity type.