3D Stacked AND-Type Flash Memory Structure
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Solution Overview
Problem
Current 3D NAND-type flash memory manufacturing processes are time-consuming and costly due to multiple lithography steps, and serially connected MOSFETs result in high read latency, limiting the number of stacked layers and increasing costs.
Innovation Solution
A 3D stacked AND-type flash memory structure with parallel connected MOSFETs, featuring horizontal planes of memory cells with charge trapping multilayers, bit lines, and source lines, allowing for independent operation of each cell and reduced manufacturing steps, enabling efficient programming and erasing methods like CHE and FN tunneling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple lithography steps are used for each memory layer in 3D NAND-type flash memory, then manufacturing precision is improved, but manufacturing cost and time increase significantly
Solution Approach 1:
The patent combines multiple lithography steps into a single lithography process by using self-aligned material deposition and pattern transfer. Word lines, bit lines, and source lines are formed simultaneously through one lithography step followed by selective etching, eliminating the need for separate lithography steps for each line type and significantly reducing manufacturing complexity and cost.
Solution Approach 2:
The patent performs preliminary material deposition and patterning to create self-aligned structures before final line formation. By pre-forming the charge trapping multilayer and using it as a mask during etching, the patent ensures precise alignment of word lines, bit lines, and source lines without requiring additional lithography steps.
2Quantity of substance
If MOSFETs are serially connected in 3D NAND-type flash memory, then storage capacity is improved, but read latency increases significantly
Solution Approach 1:
The patent segments the memory cell structure into three independent components: word lines for channel control, bit lines for charge detection, and source lines for current reference. This segmentation allows parallel operation of multiple memory cells simultaneously, enabling both high storage capacity through multiple stacked layers and low read latency through parallel read operations.
Solution Approach 2:
The patent transitions from two-dimensional planar memory to three-dimensional stacked memory by vertically stacking multiple memory layers. Each layer contains complete sets of word lines, bit lines, and source lines that operate independently and in parallel, achieving high storage capacity through vertical stacking while maintaining low read latency through parallel access to multiple layers simultaneously.
3Quantity of substance
If the number of stacked layers is increased to achieve greater storage capacity, then storage capacity is improved, but manufacturing cost increases due to process complexity
Solution Approach 1:
The patent achieves high storage capacity by stacking multiple memory layers in the vertical dimension rather than expanding in the horizontal plane. Each stacked layer is formed using the same single-lithography process, allowing scalable fabrication of 3D structures without proportionally increasing process complexity or manufacturing cost.
Solution Approach 2:
The patent creates a universal memory cell structure where word lines, bit lines, and source lines serve multiple functions across different memory layers. The same lithography and etching processes are used for all line types and all layers, enabling scalable fabrication with consistent manufacturing costs regardless of the number of stacked layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances read latency, reduces manufacturing costs, and allows for a greater number of stacked layers, supporting both one-bit and two-bit per cell operations while maintaining efficient programming and erasing capabilities.
Implementation Method 1
charge trapping multilayers alternately arranged
Implementation Method 2
efficient programming and erasing methods like CHE and FN tunneling
Implementation Method 3
efficient programming and erasing methods like CHE and FN tunneling
Data Source
AI summary
A 3D stacked AND-type flash memory structure comprises several horizontal planes of memory cells arranged in a three-dimensional array, and each horizontal plane comprising several word lines and several of charge trapping multilayers arranged alternately, and the adjacent word lines spaced apart from each other with each charge trapping multilayer interposed between; a plurality of sets of bit lines and source lines arranged alternately and disposed vertically to the horizontal planes; and a plurality of sets of channels and sets of insulation pillars arranged alternatively, and disposed perpendicularly to the horizontal planes, wherein one set of channels is sandwiched between the adjacent sets of bit lines and source lines.