Solid-State Devices TRIZ Cases

Parallel connected MOSFETs in a 3D stacked AND-type flash memory structure reduce read latency and manufacturing costs compared to serial NAND designs.

An oxidant reduces chlorine concentration in high-k dielectric layers formed via atomic layer deposition to enhance substrate adhesion.

A display device embeds ultrasonic transducers between substrates to enable fingerprint recognition.

A semiconductor light emitting element uses a second pad electrode to form a Schottky contact with the underlying layer.

Graded silicon oxide materials reinforce 3D memory pedestal channels, preventing structural damage during conductive layer formation.

A photosensor applies pulsed gate voltage to an oxide semiconductor channel for continuous light detection.

A semiconductor fin structure with a body contact connects the channel to the substrate, reducing self-heating and floating body effects.

Varying additive concentration in stacked electrode films controls the etching rate to form a through-hole with perpendicular walls and uniform diameter.

A barrier layer of W, TiW, WN, TiN, Ta, or TaN with 3.0 nm RMS roughness suppresses aluminum diffusion into the semiconductor layer.

Segmenting the gate electrode and line allows distinct material selection, while a conductive oxide relay electrode reduces parasitic capacitance.

A conductive layer between the first electrode and electron injection layer enhances electron injection efficiency in organic electroluminescent diodes.

Intermediary channels capture laterally absorbed light and guide it away from the array, resolving density-efficiency trade-offs.

Adjusting the patterned semiconductor layer area in the pixel structure compensates for feedthrough voltage differences, eliminating display frame flicker.

Multi-depth element isolation segments the FD-SOI structure to suppress leakage current and prevent short channel effects in high-density integration.

A memory transistor uses an oxide semiconductor and a second gate electrode to control threshold voltage and minimize off-state current.

An insulating isolation structure between pixel electrodes increases lateral resistance to prevent parallel voltage leakage through the optical clear adhesive.

Segmented substrate blocks allow any end connection, reducing circuit complexity for high-voltage applications.

Metal nanoparticles in a matrix absorb ambient light to enhance display contrast.

Tilted Halo ion implantation reduces source-drain overlap, lowering band-band leakage current and junction capacitance in scaled MOSFETs.

Resin members on lateral surfaces redirect light upward, reducing luminance unevenness while allowing thinner device designs compared to hemispherical lenses.

Low-k dielectric heat-insulating layer surrounds phase change memory heating electrodes to confine thermal energy.

Orthogonal routing separates data and touch sensing lines to eliminate signal interference from overlapping conductors.

A rhombic reverse fill pattern shapes metal layer slots to distribute electrical current evenly across conductor regions.

A magnetoresistance effect element detects magnetic field changes to switch electronic modes without software intervention.

Segmenting Ge concentration across layered structures prevents defects and dislocations caused by lattice stress during thermal processing.

A non-uniform tunnel barrier constricts current flow in phase change memory cells to achieve localized heating.

Polymer patterns create cavities for metal lines in magnetic tunnel junctions, preventing sub-trench formation and short-circuit risks during manufacturing.

A reverse tapered memory hole structure enables precise impurity diffusion at the select gate electrode layer interface.

A hybrid circuit integrates a GaN high electron mobility transistor with a nitride-based memristor to enable ultra-fast switching.

Via holes in insulating layers intercept crack propagation paths, preventing moisture penetration and extending OLED display lifespan.

Inorganic quantum dots replace organic layers in the blue sub pixel, resolving degradation issues while raising luminous efficiency.

Ozone pulses transform anatase titanium dioxide into rutile phase, eliminating costly annealing and mechanical stress in DRAM devices.

Localizing halo ions in end portions improves HEIP reliability while reducing GIDL leakage without increasing gate length.

A resin case wall prevents bonding material from spreading to the sub lead, securing wire connectivity and improving connection reliability.

An LED component with a minimized recess surface area improves light extraction while maintaining thermal management capabilities.

Varying microlens curvature and spacing compensates for edge light angles to ensure uniform sensitivity across the image sensor chip.

Cavity-assisted solder filling resolves high aspect ratio challenges, ensuring uniform contact hole filling and reliable chip stacking.

Staircase gate electrodes integrate insulating pads to prevent electrical shorts and eliminate costly pad removal operations in vertical memory manufacturing.

A stacked image sensor architecture integrates an upper pixel chip with a lower MRAM frame buffer to manage signal storage efficiently.

A light emitting assembly uses non-overlapping red and green phosphor layers on an LED chip to improve light conversion efficiency.

Segmenting power line width reduces radiation attenuation to shrink bezel dimensions.

An iron-doped nitride buffer layer employs a monotonic concentration gradient to suppress leakage current while maintaining high resistance.

A water-based photoresist stripper uses chain and cyclic amines to dissolve resist layers without damaging underlying thin films.

A semiconductor circuit arrangement integrates a Hall sensor and resistance element to correct voltage signals.

Applying control gate potentials to drive electron tunneling in flash memory cells with low gate coupling ratios.

A display device integrates a liquid crystal lens and touch sensor via a shared driving electrode for seamless mode switching.

Multiple spacer steps decouple feature distance from width to overcome photolithographic pitch limits and enable sub-50nm integration.

A photodetection pixel integrates a shielded temperature sensor with its avalanche diode to enable precise drive voltage control.