SOI Selecting Transistor Gate Insulation for Low Power
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Solution Overview
Problem
In semiconductor devices with single-gate MONOS memory, reducing the thickness of the gate insulating film to lower driving voltage and power consumption leads to a breakdown voltage issue between the gate electrode and source/drain regions in the selecting transistor.
Innovation Solution
The semiconductor device incorporates a selecting transistor and a memory transistor formed on an SOI substrate, with a thinner gate electrode and a drain region positioned away from the selecting gate electrode, and applies a voltage with opposite polarity to the semiconductor substrate during write operations to ensure breakdown voltage reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the gate insulating film thickness is reduced to lower driving voltage and power consumption, then power consumption is reduced, but breakdown voltage between gate electrode and source/drain regions cannot be ensured
Solution Approach 1:
The patent applies different gate insulating film thicknesses to different transistor types within the same device. Specifically, the selecting transistor has a first gate insulating film with thickness of 5-15nm (thinner for lower power), while the memory transistor has a second gate insulating film with thickness of 15-30nm (thicker for reliability). This local differentiation allows each transistor to be optimized for its specific function without compromising overall device reliability.
Solution Approach 2:
The gate insulating film structure is segmented into two distinct layers: a first gate insulating film for the selecting transistor and a second gate insulating film for the memory transistor. This segmentation enables independent optimization of film thickness for each transistor type, allowing the selecting transistor to operate at lower voltages while the memory transistor maintains adequate breakdown voltage margins.
2Ease of operation
If the gate insulating film is made thin to reduce driving voltage, then driving voltage is reduced, but breakdown voltage reliability deteriorates
Solution Approach 1:
Different gate insulating film thicknesses are assigned to different transistor regions. The selecting transistor region receives a thinner first gate insulating film (5-15nm) to enable low-voltage operation, while the memory transistor region receives a thicker second gate insulating film (15-30nm) to ensure breakdown voltage reliability. This localized quality differentiation resolves the contradiction between ease of operation and reliability.
3Ease of manufacture
If a uniform gate insulating film is used for both selecting and memory transistors, then manufacturing is simplified, but the selecting transistor cannot achieve low voltage operation without compromising reliability
Solution Approach 1:
The patent implements local quality differentiation by forming a first gate insulating film with thickness of 5-15nm in the selecting transistor region and a second gate insulating film with thickness of 15-30nm in the memory transistor region. This approach maintains manufacturing simplicity through a systematic process while enabling the selecting transistor to achieve low-voltage operation with adequate breakdown voltage margins.
Solution Approach 2:
The gate insulating film formation process is segmented into region-specific steps where different thicknesses are deposited or etched for different transistor types. This segmentation allows the selecting transistor to have a thinner film for low-voltage operation while the memory transistor has a thicker film for reliability, without significantly complicating the overall manufacturing process.
Data Source
AI summary
To make a gate insulating film of a selecting transistor coupled in series to a MONOS memory transistor thinner and to ensure insulation resistance of the gate insulating film, the selecting transistor and the memory transistor, which constitute a memory cell, are formed on an SOI substrate, and an extension region of the selecting transistor is formed to be away from a selecting gate electrode in a plan view. A drain region of the selecting transistor and a source region of the memory transistor share the same semiconductor region with each other.