SOI ICs with Dual-Side Components on Insulating Substrates
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Solution Overview
Problem
Existing integrated circuits (ICs), particularly RF ICs, face challenges in reducing size and thickness while maintaining performance due to limitations in integrating passive components, thermal conductivity, and efficient signal coupling, with prior art methods like stacked ICs experiencing issues with impedance matching and parasitic losses.
Innovation Solution
The solution involves forming ICs with components on both sides of a selected insulating substrate, such as sapphire, which improves thermal conductivity and allows for efficient integration of active and passive components, using a method that includes forming a first circuit layer on an SOI wafer and coupling it to a selected substrate, with a second circuit layer formed on the substrate's surface, enabling efficient electrical and thermal coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If passive components are placed on-chip in RF ICs, then integration is improved, but component size and parasitic impedances increase
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking by placing passive components on a separate substrate and vertically interconnecting them with active components through via holes. This dimensional change allows both active and passive components to coexist on a single IC package without occupying excessive planar area, resolving the contradiction between integration and area constraints.
2Area of stationary object
If IC size is reduced, then economy of fabrication and packaging is improved, but heat dissipation becomes more difficult
Solution Approach 1:
The patent segments the IC into multiple functional layers: active components on one substrate, passive components on another substrate, and thermal management structures including heat sinks and thermally conductive materials. This segmentation allows heat to be dissipated through dedicated thermal pathways without compromising the compact IC area, resolving the contradiction between size reduction and heat dissipation.
3Area of stationary object
If stacked IC layers are used, then IC size is reduced, but impedance matching and parasitic losses increase
Solution Approach 1:
The patent introduces intermediary elements including via holes filled with conductive material, impedance matching structures, and transition layers that mediate the electrical connection between stacked active and passive components. These intermediaries minimize parasitic losses and maintain impedance matching across layers, resolving the contradiction between size reduction and reliability.
4Productivity
If multiple IC layers are stacked, then integration density is improved, but thermal conductivity decreases
Solution Approach 1:
The patent employs composite material structures including thermally conductive epoxy, metal heat sinks, and substrates with optimized thermal pathways. These composite materials maintain high thermal conductivity despite multiple stacked layers, allowing heat to efficiently traverse the vertical structure while maintaining high integration density, thus resolving the contradiction between productivity and thermal conductivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces IC area and thickness, enhances thermal conductivity, and improves RF signal coupling, leading to more efficient and economical fabrication with improved performance for RF ICs.
Implementation Method 1
a selected substrate comprising an insulating material... improves thermal conductivity
Implementation Method 2
capacitive coupling of RF signals between devices in the active layer and the conductive silicon substrate
Data Source
AI summary
Novel integrated circuits (SOI ICs), and methods for making and mounting the ICs are disclosed. In one embodiment, an IC comprises a first circuit layer of the IC formed from an active layer of an SOI wafer. The first circuit layer is coupled to a first surface of buffer layer, and a second surface of the buffer layer is coupled to a selected substrate comprising an insulating material. The selected substrate may be selected, without limitation, from the following types: sapphire, quartz, silicon dioxide glass, piezoelectric materials, and ceramics. A second circuit layer of the IC are formed, coupled to a second surface of the selected substrate. In one embodiment of a mounted IC, the first circuit layer is coupled to contact pads on a package substrate via solder bumps or copper pillars. The second circuit layer is coupled to contact pads on the package substrate via wire bonds.