FD-SOI Semiconductor Device With Multi-Depth Isolation Layers
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Solution Overview
Problem
The challenge in semiconductor device fabrication lies in achieving higher-speed operation at lower voltages with increased integration, where existing methods struggle to effectively reduce parasitic capacitance and leakage current while maintaining efficient transistor performance.
Innovation Solution
The proposed solution involves a semiconductor device with an FD-SOI structure, comprising specific impurity regions, semiconductor layers, buried insulation layers, and element isolation layers, along with a method of fabrication that includes forming transistors on these layers to achieve reduced parasitic capacitance and leakage current, utilizing a CMOS configuration and applying body bias voltage to control threshold voltage and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If conventional semiconductor fabrication methods are used, then manufacturing process is simpler, but parasitic capacitance and leakage current cannot be effectively reduced
Solution Approach 1:
The device is segmented into multiple functional layers including first and second buried insulation layers, third and fourth semiconductor layers, and multiple element isolation layers at different depths. This segmentation isolates different functional regions and reduces parasitic interactions between adjacent components.
Solution Approach 2:
Different regions of the device are assigned different conductivity types (first and second conductivity types) and different insulation properties. The element isolation layers are strategically positioned to provide localized electrical isolation where needed, while maintaining conductivity in other regions for current flow.
2Object-affected harmful factors
If element isolation layers are formed at single depth, then fabrication process is simpler, but short channel effects cannot be effectively prevented
Solution Approach 1:
The element isolation structure is extended into the vertical dimension with isolation layers formed at multiple depths (first element isolation layer and second element isolation layer at different positions). This multi-depth approach provides comprehensive control over short channel effects by isolating channels at different vertical levels.
Solution Approach 2:
The first element isolation layer is formed before the transistors, and the second element isolation layer is formed subsequently at a different depth. This preliminary and staged formation of isolation structures allows for better control of channel effects during subsequent processing steps.
3Productivity
If integration density is increased, then device functionality is enhanced, but leakage current increases
Solution Approach 1:
Buried insulation layers are introduced as intermediary structures between the substrate and the active semiconductor regions. These insulation layers act as mediators that reduce direct electrical interaction and parasitic leakage paths, enabling higher integration without proportional increase in leakage current.
Solution Approach 2:
The device employs composite structures combining semiconductor materials of different conductivity types with insulation materials in multiple layers. This composite architecture allows dense integration of functional elements while the insulating components suppress leakage currents between adjacent high-density structures.
Data Source
AI summary
A semiconductor comprises two transistors of the first conductivity type separated from two transistors of a second conductivity type by a first element isolation layer. Further, the two transistors of the first conductivity type are separated from each other by a second element isolation layer and the two transistors of the second conductivity type are separated from each other by a third element isolation layer. In example embodiments, the second and third element isolation layers are shallower than the first element isolation layer.