Stacked Image Sensor With MRAM Frame Buffer
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Solution Overview
Problem
Current image sensors face challenges in efficiently processing and storing pixel signals, leading to potential overload and reduced performance in image processing and data handling.
Innovation Solution
The implementation of a multi-layered image sensor architecture with an upper chip containing pixels, an intermediate chip for initial image processing, and a lower chip with a frame buffer using MRAM for storing pixel signals, which includes an image signal processor and a buffer to manage and process the signals effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a frame buffer is added to store pixel signals, then the image sensor's ability to handle and process pixel signals is improved, but the device complexity increases
Solution Approach 1:
The image sensor is divided into multiple functional layers: an upper chip containing pixels for light detection, an intermediate chip for initial signal processing, and a lower chip containing the frame buffer for storage. This segmentation allows each layer to specialize in specific functions, improving overall signal processing capability while distributing complexity across separate modules.
Solution Approach 2:
The patent transitions from a single-plane sensor architecture to a three-dimensional stacked architecture with multiple chips arranged vertically. This dimensional change enables the integration of pixel array, processing units, and frame buffer in different spatial layers, allowing simultaneous operation of detection, processing, and storage functions without increasing lateral footprint.
2Productivity
If MRAM is used for frame buffer storage, then the efficiency of signal storage is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent changes the storage medium parameter from conventional memory (such as SRAM or DRAM) to MRAM (Magnetoresistive Random Access Memory). This parameter change provides non-volatile storage with higher density and potentially lower power consumption, improving storage efficiency. The MRAM is integrated into the lower chip of the stacked architecture, where it can be manufactured using specialized processes compatible with the multi-chip assembly.
3Measurement precision
If multiple storage gates/nodes are implemented per pixel, then the image quality is improved through better charge storage, but the pixel area increases
Solution Approach 1:
Instead of expanding pixel area horizontally to accommodate multiple storage gates, the patent utilizes the vertical dimension by stacking multiple chips. The pixel structures on the upper chip maintain compact footprints, while additional storage functionality is achieved through the three-layer architecture with intermediate and lower chips providing supplementary storage and processing capabilities.
Solution Approach 2:
The intermediate chip acts as a mediator between the pixel array on the upper chip and the frame buffer on the lower chip. It provides initial signal processing and temporary storage, enabling the pixel structures to remain compact while still achieving enhanced image quality through the distributed storage architecture across multiple chips.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the image sensor's ability to handle and process pixel signals, reducing overload and improving operating characteristics by utilizing MRAM for efficient signal storage and processing, thereby improving image quality and reducing processing burdens.
Implementation Method 1
a photodiode (PD). The photodiode may serve to convert incident light into electrical signal
Implementation Method 2
the frame buffer includes an MRAM
Data Source
AI summary
An image sensor comprises an upper chip including pixels; and a lower chip placed below the upper chip, wherein a pixel of the pixels includes an optical conversion element configured that light is incident on the optical conversion element, a first storage gate or a first storage node which is electrically connected to the optical conversion element and configured to store electric charge transferred from the optical conversion element during a first time interval, and a second storage gate or a second storage node which is electrically connected to the optical conversion element and configured to store the electric charge transferred from the optical conversion element during a second time interval different from the first time interval, the pixel is configured to generate a first pixel signal on the basis of the electric charge stored in the first storage gate, the lower chip includes a frame buffer.