Variable Resistance Memory Conductive Line Arrangement
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high performance and low power consumption while maintaining a compact chip size and simple interconnection structure, particularly in variable resistance memory devices.
Innovation Solution
The proposed solution involves a variable resistance memory device design with a substrate, lower and upper conductive lines, and memory cells, where the conductive lines are arranged in a specific pattern to reduce chip size and simplify interconnections, using materials like metallic materials and metal nitrides for conductive lines and chalcogenide materials for variable resistance patterns, along with switching patterns and electrode layers for memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional memory device structures are used, then data storage function is achieved, but chip size is large and interconnection structure is complex
Solution Approach 1:
The patent transitions from a planar two-dimensional memory structure to a three-dimensional stacked structure. Multiple cell stacks are vertically stacked on the substrate, with lower conductive lines in the first direction and upper conductive lines crossing in the second direction. This vertical stacking enables higher storage density within the same chip area, effectively reducing the required chip size while maintaining the interconnection structure complexity at an acceptable level through systematic arrangement.
Solution Approach 2:
The memory device is divided into multiple independent cell stacks, each containing lower conductive lines, upper conductive lines, and memory cells at their intersections. This segmentation allows modular fabrication and systematic interconnection, where each cell stack can be independently structured and connected to peripheral circuits through contact holes, simplifying the overall interconnection architecture compared to a monolithic planar structure.
2Productivity
If next-generation memory structures are adopted, then performance and power consumption are improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs a systematic sequential fabrication process where structures are prepared in advance for subsequent steps. Lower conductive lines are formed first, followed by formation of memory cells at their intersections with upper conductive line regions. Contact holes are preliminarily formed to reach lower conductive lines before final interconnection is established. This preliminary action approach enables complex 3D structures to be manufactured through manageable sequential steps, reducing overall manufacturing complexity.
Solution Approach 2:
The patent implements a nested structure where memory cells are positioned at intersections of lower and upper conductive lines within cell stacks, and multiple cell stacks are vertically nested on the substrate. Peripheral circuits are formed in regions between cell stacks or below the stacked structure. This nested arrangement allows efficient use of three-dimensional space, enabling high-density memory integration while maintaining systematic manufacturing through layer-by-layer fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables a reduced chip size and simplified interconnection structure, enhancing the performance and efficiency of variable resistance memory devices while maintaining low power consumption.
Implementation Method 1
A material or structure of such a next-generation semiconductor memory device has a resistance property that is changed by a current or voltage forced thereto
Data Source
AI summary
A variable resistance memory device includes lower conductive lines on a substrate, upper conductive lines on the lower conductive lines to cross the lower conductive lines, and memory cells between the lower conductive lines and the upper conductive lines. The lower conductive lines are extended in a first direction and are spaced apart from each other in a second direction crossing the first direction. Each of the lower conductive lines include a first line portion extended in the first direction, a second line portion offset from the first line portion in the second direction and extended in the first direction, and a connecting portion connecting the first line portion to the second line portion.