Vertical Gate Transistor Surface Area Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing UCP memory cells have a relatively large semiconductor surface area, which can be reduced to minimize the surface area of memory arrays and simplify the memory structure.
Innovation Solution
The method involves forming vertical gate transistors with a doped isolation layer, parallel trench isolations, and trench conductors that form vertical gates, allowing for the burial of selection transistors, reducing the semiconductor surface area by eliminating the need for surface-mounted selection transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional UCP memory cells with surface-mounted selection transistors are used, then the memory structure is simple and easy to manufacture, but the semiconductor surface area occupied by each memory cell is large
Solution Approach 1:
The selection transistor gate is moved from the surface plane to the vertical dimension by forming it as a deep trench conductor extending into the substrate. This dimensional transition allows the selection transistor to be buried beneath the surface, freeing up surface area while maintaining the two-transistor memory cell structure.
Solution Approach 2:
The selection transistor is nested within the substrate by forming its gate as a trench conductor that extends vertically into the substrate. The channel region and source/drain regions are positioned around this vertical gate structure, effectively nesting the transistor within the substrate volume rather than spreading it across the surface.
2Area of stationary object
If the selection transistor is buried in the substrate with a vertical gate trench, then the semiconductor surface area is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The manufacturing process is segmented into distinct sequential steps: forming parallel trench isolations to define regions, forming perpendicular trench conductors to create vertical gates, implanting dopant regions to form source and drain regions, and forming charge accumulation transistors on the surface. This segmentation makes the complex process more manageable and systematic.
Solution Approach 2:
The parallel trench isolations are formed first to pre-define the regions where vertical gate trenches and dopant regions will subsequently be formed. This preliminary structuring guides subsequent manufacturing steps and ensures proper spatial relationships between components before the actual transistor formation begins.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the semiconductor surface area occupied by memory cells, enabling more compact memory arrays with reduced size and cost while maintaining storage capacity.
Implementation Method 1
implanting, in the depth of the substrate, a doped isolation layer, to form a source region of the transistors
Implementation Method 2
etching the first conductive layer to form trench conductors in the second trenches forming vertical gates of the transistors
Implementation Method 3
implanting doped regions on each side of the second trenches to form drain regions of the transistors
Data Source
AI summary
The disclosure relates to a method of manufacturing vertical gate transistors in a semiconductor substrate, comprising implanting, in the depth of the substrate, a doped isolation layer, to form a source region of the transistors; forming, in the substrate, parallel trench isolations and second trenches perpendicular to the trench isolations, reaching the isolation layer, and isolated from the substrate by a first dielectric layer; depositing a first conductive layer on the surface of the substrate and in the second trenches; etching the first conductive layer to form the vertical gates of the transistors, and vertical gate connection pads between the extremity of the vertical gates and an edge of the substrate, while keeping a continuity zone in the first conductive layer between each connection pad and a vertical gate; and implanting doped regions on each side of the second trenches, to form drain regions of the transistors.