Reverse Tapered Memory Hole for Stable Erasing in 3D NAND
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Solution Overview
Problem
In three-dimensional stacked nonvolatile semiconductor memory devices, achieving stable threshold voltage and efficient data erasing is challenging due to the requirement for high-concentration impurity diffusion regions and the need for precise control of pore diameters in memory holes to facilitate GIDL current-based erasing methods.
Innovation Solution
The solution involves forming a nonvolatile semiconductor memory device with a specific structure where the pore diameter of the second hole at the select gate electrode layer interface is smaller than at the interlayer insulating film interface, allowing for a reverse tapered shape, which enables the formation of a high-concentration impurity region at the upper end of the select gate, enhancing the GIDL current and stabilizing the threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high-concentration impurity diffusion region is formed in the channel body layer at the upper end of the select gate to enable GIDL current-based erasing, then the erasing speed is improved, but the manufacturing precision required to control impurity distribution increases
Solution Approach 1:
The patent utilizes a porous insulating layer with controlled pore diameter to facilitate precise impurity diffusion. The pore structure allows impurities to be introduced and distributed at specific locations and concentrations, enabling the formation of high-concentration impurity regions needed for GIDL current while maintaining control over the diffusion process through pore size management
Solution Approach 2:
The patent creates localized high-concentration impurity regions specifically at the upper end of the select gate channel body layer, rather than uniform distribution throughout the entire channel. This local quality approach concentrates the impurity diffusion where it is most needed for GIDL current generation, improving erasing speed while limiting the overall manufacturing complexity
2Stability of the object's composition
If the pore diameter of the second hole is made smaller at the select gate electrode layer interface than at the interlayer insulating film interface to create a reverse tapered shape, then the threshold voltage stability is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent introduces asymmetry in the pore diameter profile of the second hole, creating a reverse tapered shape where the pore diameter varies along the depth. Specifically, the pore diameter at the select gate electrode layer interface is made smaller than at the interlayer insulating film interface. This asymmetric pore structure enables better control over impurity diffusion profiles and electric field distribution, leading to improved threshold voltage stability
Solution Approach 2:
The patent changes the pore diameter parameter along the depth of the second hole to create the reverse tapered shape. By varying this geometric parameter, the patent optimizes the electric field distribution and impurity diffusion characteristics, achieving stable threshold voltage while managing the manufacturing complexity through controlled parameter variation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the speed and stability of the erasing operation by ensuring accurate impurity distribution and maintaining a stable threshold voltage, thereby enhancing the overall performance of the memory device.
Implementation Method 1
a gate insulating film provided on a side wall of a second hole communicating with the first hole and penetrating the second stacked body and the interlayer insulating film... a memory film provided on a side wall of a first hole penetrating the first stacked body
Implementation Method 2
a second channel body layer provided inside the gate insulating film in the second hole, and connected to the first channel body layer
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device includes: a first stacked body; a memory film; a first channel body layer provided inside the memory film; an interlayer insulating film provided on the first stacked body; a second stacked body having a select gate electrode layer, and a second insulating layer; a gate insulating film provided on a side wall of a second hole communicating with the first hole and penetrating the second stacked body and the interlayer insulating film in a stacking direction of the second stacked body; and a second channel body layer provided inside the gate insulating film in the second hole. A first pore diameter of the second hole at an upper end of the select gate electrode layer is smaller than a second pore diameter of the second hole at an lower end of the select gate electrode layer.