Ferroelectric Gate Dielectric Integration for FERAM and CMOS Logic
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Solution Overview
Problem
The semiconductor industry faces challenges in integrating high-density, low-power, and cost-effective non-volatile memory and logic circuits within a single chip, particularly in achieving efficient manufacturing processes for ferroelectric random access memory (FERAM) and complementary metal-oxide-semiconductor (CMOS) logic circuits.
Innovation Solution
The integration of 1-transistor type FERAM cells and CMOS logic circuits on a single semiconductor chip, utilizing a ferroelectric material layer as a gate dielectric, with adjustable thicknesses of insulating layers to optimize operational voltages and manufacturing efficiency, and employing gate replacement technology to form metal gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FERAM cells and CMOS logic circuits are integrated on a single chip, then device density and functionality are improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges FERAM and CMOS logic circuit fabrication into a unified process flow. By integrating the formation of ferroelectric memory cells and CMOS logic transistors within the same manufacturing sequence, the patent achieves high device density while managing manufacturing complexity through process consolidation rather than separate fabrication lines.
Solution Approach 2:
The patent employs universal process steps that serve multiple functions: the same gate dielectric formation, source/drain region creation, and interlayer dielectric deposition processes are used for both FERAM cells and CMOS logic circuits. This multi-functionality approach reduces the number of dedicated process steps needed, thereby managing manufacturing complexity while achieving high integration density.
2Adaptability or versatility
If different insulating layer thicknesses are used for FERAM and CMOS areas, then operational voltage optimization is improved, but process complexity increases
Solution Approach 1:
The patent applies local quality by forming different thicknesses of gate dielectric layers and interlayer dielectric layers in different regions of the chip. Specifically, the FERAM area receives a first thickness of insulating material while the CMOS logic area receives a second, different thickness. This regional differentiation optimizes operational voltages for each circuit type while the patent manages process complexity through selective area processing and localized deposition techniques.
3Reliability
If gate replacement technology is employed, then transistor performance is improved, but manufacturing steps increase
Solution Approach 1:
The patent implements preliminary action by forming initial gate structures (such as polysilicon gates or metal gates) during the standard CMOS fabrication process, then replacing these preliminary gates with optimized metal gate structures in a subsequent dedicated gate replacement step. This preliminary gate formation allows the rest of the fabrication process to proceed with simpler structures, while the performance-enhancing metal gates are added later to optimize transistor characteristics without disrupting the main fabrication flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of semiconductor devices with reduced manufacturing costs and efficient operation of both FERAM and logic circuits, allowing for high-density, low-power consumption, and cost-effective integration of non-volatile memory and logic functions on a single chip.
Implementation Method 1
utilizing a ferroelectric material layer as a gate dielectric
Data Source
AI summary
A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.