Gate Injection for Low Coupling Ratio Flash Memory
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Solution Overview
Problem
As flash memory devices are scaled down, maintaining a high gate coupling ratio for efficient channel injection becomes difficult, leading to reduced reliability and increased inter-cell interference due to low electric fields and FinFET-like structures with naturally low gate coupling capacitance.
Innovation Solution
A method is implemented where a gate coupling ratio of less than 0.4 is maintained by applying a potential across the control gate for electron injection or ejection to the floating gate, suited for n- and p-Channel cells, particularly using bulk-tied FinFET-like structures, which allows scalability down to below 20 nm and reduces inter-cell interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FinFET-like structures are used to improve device short-channel characteristics, then device performance is improved, but gate coupling ratio decreases below 0.3
Solution Approach 1:
The patent changes the operational parameters by applying specific potentials to the control gate and bulk to achieve efficient electron injection despite the low GCR. By adjusting voltage parameters (Vcg, Vb, Vs, Vd) during program and erase operations, the method compensates for the structurally-induced low coupling ratio while maintaining reliable operation.
2Productivity
If device density is increased, then memory capacity is improved, but inter-floating gate coupling increases causing cell interference
Solution Approach 1:
The bulk serves as an intermediary element that, when properly biased, shields the channel from unwanted electric field coupling between adjacent floating gates. By controlling the bulk potential, the method reduces the harmful capacitive coupling between neighboring cells while maintaining the high-density array structure.
3Productivity
If gate coupling ratio is maximized for efficient channel injection, then injection efficiency is improved, but device scalability to below 45 nm is limited
Solution Approach 1:
Instead of trying to maximize GCR through structural modifications that would prevent scaling, the patent inverts the approach by accepting the low GCR as inevitable at small nodes and compensating through electrical parameter control. The method uses optimized voltage application sequences and bulk biasing to achieve efficient injection despite the inherently low coupling ratio at scaled dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the reliability and endurance of flash memory devices by maintaining efficient Fowler-Nordheim tunneling and minimizing inter-cell interference, enabling scalable operation down to technology nodes smaller than 20 nm with controlled coupling ratios and interference.
Implementation Method 1
Electrons undergo Fowler-Nordheim (FN) tunneling and are transferred from the channel to the floating gate, and vice-versa, during operation.
Implementation Method 2
A method of performing an operation on a flash memory cell device is provided when a gate coupling ratio between a floating gate and a control gate is less than 0.4. A potential is required to be applied across the control gate. Electrons are either injected to the floating gate from the control gate or ejected from the floating gate to the control gate.
Data Source
AI summary
A method of performing an operation on a flash memory cell device, used when a gate coupling ratio between a floating gate and a control gate of less than 0.4. A potential is required to be applied across the control gate. Electrons are either injected to the floating gate from the control gate or ejected from the floating gate to the control gate. The operation associated with the injection or the ejection is determined by the nature of a silicon channel provided in the device. Devices using a bulk-tied FinFET-like structure are particularly suited to this method. The method is also particularly suited for use on cells in a NAND array.