Variable Resistance Memory Stack Capping Layer Impurity Removal

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Solution Overview

Problem

Current semiconductor memory devices face challenges in achieving improved operational characteristics and reliability, particularly in maintaining the integrity of variable resistance patterns during the fabrication process, which affects their switching performance and data storage capabilities.

Innovation Solution

The method involves forming stack structures with variable resistance patterns, applying capping layers with impurities, and then treating these layers with ultraviolet light or plasma to remove impurities and densify the gap fill layer, thereby enhancing the reliability and performance of the semiconductor memory devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If capping layers with impurities are formed on stack structures, then the variable resistance material is protected during fabrication, but the impurities cause characteristic degradation of the variable resistance material

Engineering Contradiction:
Improveintegrity of variable resistance materialVSAvoidcharacteristic degradation
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

A gap fill layer is introduced as an intermediary between the capping layers and the variable resistance material. This gap fill layer acts as a buffer that prevents direct contact between impurities in the capping layers and the variable resistance material, thereby protecting the material characteristics while maintaining the protective function of the capping layers

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The harmful impurities are extracted from the capping layers through plasma treatment or thermal annealing processes. By removing the impurities after the capping layers are formed, the protective function is maintained while the harmful effects are eliminated, resolving the contradiction between protection and material integrity

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If the gap fill layer is not densified, then the fabrication process is simpler, but the operational characteristics and reliability of memory cells are improved

Engineering Contradiction:
Improveoperational characteristics of memory cellsVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gap fill layer formation and densification processes are merged with the existing fabrication sequence. The gap fill layer is formed using standard deposition techniques already present in the manufacturing line, and densification is achieved through plasma treatment or thermal annealing that can be integrated into existing process steps, minimizing additional complexity while improving reliability

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the operational characteristics and reliability of memory cells by preventing characteristic degradation of the variable resistance material, ensuring effective switching and data storage while maintaining the integrity of the memory device components.

Implementation Method 1

removing the impurity from the capping layers and densifying the gap fill layer by irradiating the capping layers and the gap fill layer with ultraviolet light

Methodology Applied
Scientific EffectUltraviolet light irradiation: Light

Implementation Method 2

removing the impurity from the capping layers and densifying the gap fill layer by plasma-treating the capping layers and the gap fill layer

Methodology Applied
Scientific EffectPlasma treatment: Plasma

Data Source

PatentUS10879461B2Electronic device and method for fabricating the same
Publication Date: 2020.12.29 SK HYNIX INC
  • US10879461B2 patent drawing
  • US10879461B2 patent drawing
  • US10879461B2 patent drawing

AI summary

In a method for fabricating an electronic device including a semiconductor memory, the method includes: forming stack structures, each of the stack structures including a variable resistance pattern; forming capping layers on the stack structures, the capping layers including an impurity; forming a gap fill layer between the stack structures; and removing the impurity from the capping layers and densifying the gap fill layer by irradiating the capping layers and the gap fill layer with ultraviolet light.