Air Gap Between Gate Structures Reduces RC Delay

Solution Overview

Problem

As semiconductor device integration advances, the resistor-capacitor delay (RC delay) and electrical interference between components limit the speed and reliability of integrated circuits, necessitating a solution to enhance efficiency.

Innovation Solution

The method involves forming an air gap between gate structures by creating a first dielectric layer with a groove, covering it with an intermediate layer, forming openings, and removing the dielectric layer to define an air gap, which prevents RC delay and improves electrical interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the size of semiconductor device is reduced according to design rules, then integration is improved, but RC delay and electrical interference increase

Engineering Contradiction:

ImproveintegrationVSAvoidRC delay

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent extracts the problematic dielectric material between adjacent gate structures and replaces it with an air gap. By removing the solid dielectric layer from the region between gate structures and filling with air (vacuum), the patent eliminates the source of RC delay while maintaining the compact integrated structure. This extraction approach directly addresses the contradiction by removing the harmful dielectric material that causes signal delay in highly integrated devices.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the physical parameter of the material between gate structures from solid dielectric to air (gas phase). This parameter change involves modifying the permittivity and conductivity characteristics of the intervening material, thereby reducing capacitive coupling and resistive effects between adjacent gates. The air gap provides low dielectric constant (k≈1) compared to traditional dielectric materials, directly reducing RC delay in the scaled-down integrated structure.

Inventive Principle:

Principle #35Parameter changes

2Productivity

If the size of semiconductor device is reduced according to design rules, then integration is improved, but electrical interference increases

Engineering Contradiction:

ImproveintegrationVSAvoidelectrical interference

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the problematic dielectric material between adjacent gate structures and replaces it with an air gap. By removing the solid dielectric layer from the region between gate structures and filling with air (vacuum), the patent eliminates the source of RC delay while maintaining the compact integrated structure. This extraction approach directly addresses the contradiction by removing the harmful dielectric material that causes signal delay in highly integrated devices.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the physical parameter of the material between gate structures from solid dielectric to air (gas phase). This parameter change involves modifying the permittivity and conductivity characteristics of the intervening material, thereby reducing capacitive coupling and resistive effects between adjacent gates. The air gap provides low dielectric constant (k≈1) compared to traditional dielectric materials, directly reducing RC delay in the scaled-down integrated structure.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If an air gap is formed between gate structures, then RC delay is reduced, but manufacturing complexity increases

Engineering Contradiction:

ImproveRC delayVSAvoidmanufacturing process

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by forming the air gap structure during the fabrication process before final device operation. The method involves creating openings in the dielectric layer and filling with air (or leaving voids) during manufacturing, rather than attempting to create air gaps after device assembly. This preliminary formation of air gaps during fabrication simplifies the overall process compared to post-manufacturing techniques.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent replaces complex mechanical or chemical etching methods with a simpler physical vapor deposition or plasma-based approach to form the air gap structure. By using deposition techniques to create the dielectric layer with built-in voids or by using plasma etching to selectively remove material and leave air gaps, the manufacturing process becomes more controllable and less mechanically complex than traditional mechanical drilling or chemical etching methods.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS9337208B2Semiconductor memory array with air gaps between adjacent gate structures and method of manufacturing the same

Publication Date: 2016.05.10 MACRONIX INTERNATIONAL CO LTD

AI summary

A method of manufacturing a semiconductor device is provided. Gate structures are formed on a substrate, and a first dielectric layer having grooves is formed between two adjacent gate structures. An upper surface of the first dielectric layer is lower than an upper surface of the gate structures. Afterwards, an intermediate layer is formed to cover the gate structures, the first dielectric layer, and the grooves, and openings are formed therein. Each opening is formed between two adjacent gate structures, and the first dielectric layer is removed through the opening. Next, a second dielectric layer is formed on the intermediate layer, so as to define an air gap between two adjacent gate structures. Furthermore, a semiconductor device is provided.