Vertical Memory Gate Electrode Insulation Design
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Solution Overview
Problem
The removal of insulation pads in VNAND flash memory devices is time-consuming and costly, leading to increased production costs due to the potential for electrical shorts caused by metal gates, which necessitates their removal.
Innovation Solution
A vertical memory device design featuring a staircase-shaped gate electrode structure with conductive pads and insulation pads of the same material, allowing for electrical insulation and avoiding the need for pad removal, thus reducing production costs and time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal gate is used, then electrical insulation is improved, but electrical short occurs requiring pad removal
Solution Approach 1:
The patent introduces an insulating pad made of silicon nitride as an intermediary layer between the metal gate and the substrate. This mediator prevents direct electrical contact that would cause shorts, while allowing the metal gate to maintain its superior electrical insulation properties. The insulating pad acts as a buffer layer that resolves the conflict between achieving good electrical insulation and preventing harmful electrical shorts.
Solution Approach 2:
The gate structure employs a composite material approach by combining metal (for gate functionality) with silicon nitride insulating material (for electrical isolation). This composite structure integrates the advantages of both materials: the metal provides excellent electrical insulation characteristics, while the silicon nitride layer prevents electrical shorts to the substrate. This composite design eliminates the need for pad removal while maintaining reliability.
2Reliability
If insulation pad removal is performed, then electrical short is prevented, but manufacturing time and cost increase
Solution Approach 1:
The insulating pad is formed as part of the gate structure during the manufacturing process itself, before final device assembly. By incorporating the silicon nitride insulating layer into the gate formation steps, the electrical isolation function is established in advance, eliminating the need for subsequent pad removal operations. This preliminary integration of the insulating function saves significant manufacturing time.
Solution Approach 2:
The patent merges the insulating pad formation with the gate electrode fabrication process. The silicon nitride layer is deposited and patterned together with the metal gate structure, combining multiple functions (gate functionality and electrical isolation) into a single integrated structure. This merging eliminates separate pad removal steps, reducing both time and cost while maintaining electrical reliability.
3Reliability
If insulation pad removal is performed, then electrical short is prevented, but manufacturing cost increases
Solution Approach 1:
The insulating pad is formed during the gate fabrication process itself, using standard deposition and patterning techniques already employed in manufacturing. By establishing the electrical isolation function in advance during normal production steps, the need for additional expensive removal operations is eliminated, reducing overall manufacturing cost while ensuring reliability.
Solution Approach 2:
The gate electrode and insulating pad are fabricated as an integrated structure in a single manufacturing sequence. The silicon nitride layer is deposited and patterned together with the metal gate, combining multiple functions into one process flow. This merging eliminates separate pad removal steps, reducing both time and cost while maintaining electrical isolation and preventing shorts.
Data Source
AI summary
A vertical memory device including: a substrate including a first and second regions; gate electrodes spaced apart from each other in a first direction, each of the gate electrodes extending in a second direction on the first and second regions, and the gate electrode are stacked on the second region; a channel extending in the first direction on the first region, the channel extending through the gate electrodes; a first conductive structure on an end portion of a first gate electrode, the end portion on the second region, the first gate electrode being disposed at a lowermost level; and a second conductive structure spaced apart from the first conductive structure in the second direction on the second region, the second conductive structure not overlapping the first gate electrode in the first direction and being disposed at a height different from that of the first conductive structure.