Fabricating Diode Arrays for Non-Volatile Memory
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Solution Overview
Problem
Conventional diodes in selector arrays for non-volatile memories like RRAM and PCRAM suffer from undesirable bipolar effects due to parasitic p-n junctions with the substrate and face challenges in size reduction and etch process control, particularly due to precise alignment requirements and form factor variations.
Innovation Solution
A method for fabricating diodes that involves forming an initial structure with insulating and conductive silicon layers on a semiconductor substrate, etching in orthogonal directions to create insulated diode structures, and connecting them to memory cells via metal contacts, eliminating direct substrate contact and reducing masking steps for improved control and alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If diodes are directly formed in a semiconductor substrate, then the fabrication process is simplified, but parasitic bipolar effects occur due to direct contact with the substrate
Solution Approach 1:
An insulating layer is introduced between the diode structures and the semiconductor substrate. This intermediary layer prevents direct electrical contact, thereby eliminating parasitic bipolar effects while maintaining the overall fabrication simplicity. The insulating layer acts as a mediator that isolates the diodes from the substrate without complicating the process flow.
2Ease of manufacture
If conventional etching processes are used for diode fabrication, then the process is straightforward, but precise alignment and form factor control become difficult at reduced dimensions
Solution Approach 1:
The etching process is divided into multiple sequential steps, each creating specific structures ( trenches, pads, contact holes) with controlled dimensions. By segmenting the etching into discrete stages with intermediate structures, precise alignment and form factor control are achieved at reduced dimensions while maintaining process simplicity.
3Area of moving object
If diode arrays are miniaturized to reduce surface area, then the memory density increases, but etch process control and alignment precision deteriorate
Solution Approach 1:
The patent transitions from planar diode structures to vertically stacked three-dimensional structures. By utilizing the vertical dimension with multiple layers (first diode layer, second diode layer, insulating layers), the selector array achieves higher density on a reduced surface area while the multi-layer architecture provides inherent alignment references that maintain etch process control at miniaturized dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach eliminates parasitic bipolar effects, enhances etch process control, and minimizes the surface area of the selector array, making it compatible with existing non-volatile memory technologies while allowing for reduced dimension diode formation without critical alignment issues.
Implementation Method 1
the etching of the buffer layer in strips running in a first direction
Implementation Method 2
the etching down to the insulating layer of the second layer of silicon, of the strips of the buffer layer and of the first layer of silicon
Implementation Method 3
the removal, by etching in the second layer of silicon and down to the buffer layer, of strips running in the first direction
Data Source
AI summary
The array of diodes comprises a matrix plane of diodes arranged according to columns in a first direction and according to rows in a second direction orthogonal to the first direction. The said diodes comprise a cathode region of a first type of conductivity and an anode region of a second type of conductivity, the said cathode and anode regions being superposed and disposed on an insulating layer situated on top of a semiconductor substrate.