Dummy Gate Structure Formation in Semiconductor-on-Insulator
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Solution Overview
Problem
The formation of dummy gate structures over shallow trench isolation structures in integrated circuits is hindered by the non-planar topography of these structures, leading to issues such as high-k or metal gate footing and limitations in pitch between adjacent gate and dummy gate structures.
Innovation Solution
The method involves forming dummy gate structures without high-k materials or workfunction adjustment metals over continuous active regions in semiconductor-on-insulator (SOI) structures, using gate insulation layers like silicon dioxide and polysilicon or amorphous silicon gate electrodes, which are doped to maintain transistors in an OFF-state for electrical insulation, thereby avoiding the topography-related issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy gate structures are formed over shallow trench isolation structures with high-k materials and workfunction adjustment metals, then the spacing uniformity between gate structures and dummy gate structures is improved, but the topography of shallow trench isolation structures causes high-k footing and patterning difficulties
Solution Approach 1:
The patent extracts and removes the problematic high-k material and workfunction adjustment metal layers from the dummy gate structure formation process. Instead of forming complete gate stacks over shallow trench isolation structures, the method selectively removes these materials from dummy gate regions, eliminating the source of high-k footing while maintaining the necessary spacing uniformity for photolithography patterning.
Solution Approach 2:
The patent inverts the conventional approach by first forming the high-k material and workfunction adjustment metal layers across the entire substrate, then selectively removing them from dummy gate regions rather than attempting to form them only in transistor gate regions. This inversion simplifies the process by avoiding the need to pattern these materials over non-planar shallow trench isolation structures.
2Manufacturing precision
If dummy gate structures are formed over shallow trench isolation structures, then spacing uniformity is improved, but the non-planar topography increases the likelihood of high-k footing and limits pitch between structures
Solution Approach 1:
The patent extracts the problematic topography by removing the shallow trench isolation structures and replacing them with a planarized dielectric layer. This eliminates the non-planar surface that causes patterning difficulties and high-k footing, while maintaining the spacing uniformity needed for dimensional accuracy in photolithography processes.
Solution Approach 2:
The patent changes the physical state and properties of the isolation layer by replacing the non-planar shallow trench isolation structure with a planarized dielectric layer formed through deposition and chemical mechanical polishing. This parameter change from non-planar to planar topology resolves the topography complexity while preserving spacing uniformity.
3Reliability
If high-k materials are used in gate insulation layers to reduce leakage currents, then the capacity between gate electrode and channel region is improved, but the non-planar topography causes high-k footing
Solution Approach 1:
The patent extracts the high-k material and workfunction adjustment metal from the dummy gate structure formation process, applying these materials only to transistor gate regions where they are needed for leakage current reduction. This selective application maintains the electrical benefits in active devices while eliminating the high-k footing problem in dummy gate regions.
Solution Approach 2:
The patent applies different material compositions to different regions: high-k materials and workfunction adjustment metals are applied only to transistor gate regions where they provide leakage current reduction, while dummy gate regions use simpler insulation layers. This local differentiation maintains reliability benefits without introducing manufacturing defects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the likelihood of high-k footing and pitch limitations, enhancing the uniformity and accuracy of dummy gate formation while providing effective electrical insulation between transistors.
Implementation Method 1
forming a first material stack above a first transistor region, a second transistor region, and a dummy gate region of a semiconductor structure, wherein the first material stack includes a high-k material layer and a workfunction adjustment metal layer
Implementation Method 2
a patterned photoresist mask is formed above the protection layer, wherein the patterned photoresist mask covers the second portions of the protection layer and exposes the first portion of the protection layer
Implementation Method 3
one or more etch processes are performed through the patterned photoresist mask to remove the first portion of the protection layer and to remove the first portion of the first material stack from above the dummy gate region
Implementation Method 4
polysilicon or amorphous silicon gate electrodes, which are doped to maintain transistors in an OFF-state for electrical insulation
Data Source
AI summary
A method includes forming a first material stack above a first transistor region, a second transistor region, and a dummy gate region of a semiconductor structure, the first material stack including a high-k material layer and a workfunction adjustment metal layer. The first material stack is patterned to remove a first portion of the first material stack from above the dummy gate region while leaving second portions of the first material stack above the first and second transistor regions. A gate electrode stack is formed above the first and second transistor regions and above the dummy gate region, and the gate electrode stack and the remaining second portions of the first material stack are patterned to form a first gate structure above the first transistor region, a second gate structure above the second transistor region, and a dummy gate structure above the dummy gate region.