3D Stacked Capacitor Reduces Chip Surface Area
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Solution Overview
Problem
Conventional storage devices face challenges in minimizing the occupation area of the circuit region due to the large size of two-dimensional capacitors, which limits their integration and efficiency.
Innovation Solution
The design incorporates a capacitor with three-dimensionally distributed capacitances, utilizing columnar conductors and electrode layers stacked in a specific configuration to reduce the chip surface area occupied by the capacitor, allowing for reduced size and increased integration with memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If two-dimensional capacitors are used in conventional storage devices, then the capacitor structure is simple and easy to manufacture, but the occupation area of the circuit region becomes large
Solution Approach 1:
The patent transitions from a two-dimensional capacitor layout to a three-dimensional structure by stacking multiple electrode layers (first electrode layer, second electrode layer, third electrode layer) vertically. This dimensional change allows the capacitor to achieve the required capacitance value while occupying significantly less chip surface area, directly resolving the technical contradiction between capacitor area and structure complexity.
Solution Approach 2:
The patent implements a nested structure where multiple electrode layers are stacked within a compact vertical space. The first electrode layer, second electrode layer, and third electrode layer are arranged in a nested configuration with insulating layers between them, allowing the capacitor to fit into a smaller footprint while maintaining the necessary electrical properties.
2Area of stationary object
If three-dimensional capacitor structure is implemented, then the occupation area is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The capacitor structure is segmented into distinct functional layers: first electrode layer, first insulating layer, second electrode layer, second insulating layer, and third electrode layer. Each layer is formed through separate manufacturing steps, allowing for precise control and inspection of each component while maintaining overall manufacturing feasibility through modular processing.
Solution Approach 2:
The patent changes the physical parameters of the capacitor by transitioning from planar electrode arrangements to vertically stacked configurations. The electrode layers are formed with specific thicknesses and areas that, when stacked, achieve the target capacitance value while reducing the horizontal footprint. This parameter transformation enables area reduction without proportionally increasing manufacturing complexity.
Data Source
AI summary
A capacitor includes a plurality of first electrode layers stacked in a first direction, a first conductor extending in the first direction through the plurality of first electrode layers, and a first insulating layer extending in the first direction along the first conductor and located between the first conductor and the plurality of first electrode layers. The capacitor includes a first capacitance provided between the first conductor and the plurality of first electrode layers.