3D Stacked Capacitor for Charge Pump Area Efficiency
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Solution Overview
Problem
In integrated circuit die, capacitors used in charge pump circuits for non-volatile memory devices occupy significant space due to their unscalable nature as technology scales down, limiting the increase in capacitance within a given volume.
Innovation Solution
A novel capacitor design with multiple electrodes in different planes, capacitively coupled and electrically connected, increasing total capacitance by combining capacitances between and within layers, optimized for use in charge pump circuits to enhance voltage pumping efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional capacitor is used in a charge pump circuit, then the circuit can store and transfer charges, but the capacitor occupies a large area on the integrated circuit die
Solution Approach 1:
The patent transitions from a conventional planar capacitor structure to a three-dimensional stacked capacitor structure with multiple electrodes arranged in different planes. The capacitor includes a first electrode in a first plane, a second electrode in a second plane, and a third electrode in a third plane, with insulating layers between them. This vertical stacking arrangement increases the effective capacitance area without proportionally increasing the die area, thereby resolving the contradiction between reducing capacitor area and maintaining capacitance.
2Productivity
If the scale of integration increases for active elements, then more transistors can be placed on the die, but passive elements such as capacitors take up a greater percentage of the die real estate
Solution Approach 1:
As integration scale increases and more active elements are placed on the die, the patent employs a vertically stacked capacitor structure that utilizes the third dimension (height) to provide additional capacitance. The multiple planes of electrodes stacked vertically increase the effective capacitance area without proportionally increasing the horizontal die area, allowing capacitors to maintain their real estate percentage even as integration scale increases.
Solution Approach 2:
The capacitor structure embeds multiple electrodes and insulating layers within each other in a nested arrangement. The first electrode is surrounded by insulating material, which is in turn surrounded by the second electrode, and so on. This nested configuration maximizes the use of available space within the capacitor structure, increasing capacitance without proportionally increasing the external dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively increases capacitance in a smaller volume, addressing the space constraints and improving the efficiency of charge pump circuits in non-volatile memory devices by optimizing the layout and connectivity of electrodes.
Implementation Method 1
A second electrode is adjacent to and spaced apart from the first electrode in the first plane and is capacitively coupled thereto. A third electrode is in a second plane, spaced apart from the first plane and is capacitively coupled to the first electrode.
Data Source
AI summary
A novel capacitor for use in a charge pump circuit has a substrate with a planar surface. A first electrode is in a first plane spaced apart from the planar surface. A second electrode is adjacent to and is spaced apart from the first electrode in the first plane and is capacitively coupled thereto. A third electrode is in a second plane, spaced apart from the first plane and is capacitively coupled to the first electrode. A fourth electrode is adjacent to and spaced apart from the third electrode in the second plane and is capacitively coupled to the third electrode and capacitively coupled to the second electrode. The first and fourth electrodes are electrically connected together and the second and third electrodes are electrically connected together. In addition, a cylindrical shape electrode, and a great wall electrode, and charge pump capacitor-by-pattern-filling is disclosed. A charge pump circuit using the foregoing described capacitor has a plurality of transistors for charging the capacitor and discharging the capacitor thereby increasing the voltage of the charge pump circuit.