3D Stacked Die Testing via Universal Signal Routing Logic
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Solution Overview
Problem
Conventional systems face challenges in testing 3D stacked IC dies due to lack of direct access for controllers on printed circuit boards, requiring complex and non-standard hardware that increases design and testing complexities, costs, and defect rates.
Innovation Solution
A secondary die test interface module with simple logic operations is used to selectively route test signals between dies in a 3D stack, allowing each die to be tested by an external component without additional hardware complexity, using the same test signal routing logic across all dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex non-standard hardware is used to enable testing of 3D stacked dies, then testing capability is improved, but device complexity and cost increase
Solution Approach 1:
The patent implements a universal test signal routing logic that can be integrated into standard CMOS processes, allowing the same hardware structure to perform multiple testing functions across different dies in the stack. This eliminates the need for complex non-standard hardware by using a standardized interface that can route test signals to any die in the 3D stack through sequential access mechanisms.
Solution Approach 2:
The patent introduces an intermediary test signal routing logic layer that mediates between the external controller and the individual dies in the stack. This routing logic acts as a mediator that can direct test signals to specific dies and route test data back to the controller, eliminating the need for direct complex hardware connections to each die while maintaining full testing capability.
2Reliability
If complex non-standard hardware is implemented for 3D die testing, then testing capability is improved, but manufacturing cost increases
Solution Approach 1:
The universal test signal routing logic designed in the patent can be manufactured using standard CMOS processes, eliminating the need for expensive non-standard hardware manufacturing. The same routing structure serves all dies in the stack, reducing per-die testing hardware cost while maintaining full testing capability across the 3D stacked structure.
3Reliability
If complex non-standard hardware is used for testing, then testing capability is improved, but defect rates increase
Solution Approach 1:
By using a universal test signal routing logic that can be integrated into standard CMOS manufacturing processes, the patent reduces the introduction of defects associated with complex non-standard hardware. The standardized interface and routing structure minimize manufacturing variability and potential defect sources while maintaining comprehensive testing capability.
4Productivity
If direct access to each die is provided for testing, then testing efficiency is improved, but device complexity increases
Solution Approach 1:
The patent introduces a test signal routing logic intermediary that enables efficient access to individual dies without requiring direct physical connections to each die. The routing logic sequentially directs test signals to the target die and routes test data back to the controller, achieving testing efficiency comparable to direct access while maintaining a simpler unified access structure.
Data Source
AI summary
Methods and systems are provided for testing three-dimensional (3D) stacked dies of integrated circuits (ICs). The methods and systems receive, by test signal routing logic implemented on a first die, a first die test signal, the test signal routing logic operating in an elevate mode or turn mode. The methods and systems receive a second die test signal from a second die and route the first die test signal to an external device in the turn mode. The methods and systems route the second die test signal received from the second die to the external device in the elevate mode.