Digital Circuit Testing TRIZ Cases
- Semiconductor Test Interface Circuitry SMU Compliance Testing
This case uses SMU and DPS resources to test DIH switches, alarms, connectivity, and decoupling capacitance before device testing.
- Functional Circuit Block Harvesting for Multi-Platform Power and Noise Control
This case shows how post-boot block harvesting configures SoCs for multiple platforms while improving yield and limiting power and noise.
- Non-Destructive Signal Authentication for Counterfeit Electronic Components
Signal injection across multiple access points and machine-learning profiles authenticate components without destructive testing.
- TAP Controller Self-Diagnostics for Precise JTAG Error Localization
An API displays voltage, GPIO, high-speed, and JTAG signals so engineers can distinguish TAP controller faults from external errors.
- Component Die VBIST Engine for Independent Early Validation
A configurable VBIST engine generates, routes, and validates test streams for subsidiary dies before the main die is available.
- Two-Chip Shared Memory Access with Voltage Arbitration
Master-slave pins and state switching coordinate shared memory access between chips, reducing hardware cost, power use, and conflicts.
- Custom Wrapper Cells for At-Speed Testing of Non-Scannable Elements
Custom wrapper cells use the functional clock to test synchronous interfaces and non-scannable sequential elements at speed.
- Hierarchical IC Test Pattern Validation Without Full Netlist Simulation
Compare propagated block-level signals with sub-block stimuli and responses to cut simulation time and memory needs.
- Optical Wafer-Scale Photodiode Bandwidth Testing Without RF Equipment
An all-optical test biases photodiodes, converts AC response to resistor heat, and uses an interferometer to infer bandwidth.
- Chiplet Interconnect Self-Repair for Short Faults Using BIST
This case uses BIST and programmable multiplexers to recover chiplet links from short faults without added repair hardware.
- Scribe-Line Delay Circuit for Sequential Testing Without Bus Collisions
A scribe-line testing circuit staggers trigger signals across electrical devices to prevent data-bus output collisions.
- Latch Circuit Testing with Counter-Based Defect Detection
A counter, comparison circuit, and determination circuit identify latch defects for more reliable memory testing.
- Neural Processing Unit Runtime Testing for Defect Isolation
Test wrappers let an in-system tester check idle NPU components during runtime, isolating faults without full system shutdown.
- Timed Autonomous Electronic Device Testing With Result Logging
A server schedules test instructions, while the device checks system time, controls target units, and records results.
- Functional Circuit Block Harvesting via Programmable Gating
This case uses programmable power and clock gating to disable unused IC blocks, reducing static power and spurious noise across platforms.