Latch Circuit Testing with Counter-Based Defect Detection
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Solution Overview
Problem
Existing memory devices face challenges in accurately determining defects in their latches, which can deteriorate the reliability of the device if left undetected.
Innovation Solution
A test device is introduced that includes a counter to output test data to a latch circuit, a comparison circuit to compare the test data with the latch output, and a determination circuit to generate a defect determination value based on the comparison signal, enabling precise detection of latch defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a test device is introduced to detect latch defects, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The test device is segmented into three functional modules: a counter to generate test data, a comparison circuit to compare test data with latch output, and a determination circuit to generate defect determination values. This segmentation allows each module to perform a specific function, improving measurement precision while keeping the overall device complexity manageable through modular design.
Solution Approach 2:
The test device is designed to be universally applicable to multiple latches within a memory device. The counter, comparison circuit, and determination circuit can be reused to test different latches, making the device multi-functional and reducing the need for separate testing mechanisms for each latch, thereby balancing measurement precision with device complexity.
2Reliability
If test data is continuously increased and compared, then reliability is improved, but loss of time increases
Solution Approach 1:
The counter continuously increases test data in advance, preparing a sequence of test values before they are needed for comparison. This preliminary action allows the comparison circuit to immediately compare pre-prepared test data with latch output without waiting for data generation, improving reliability assessment while reducing the time lost during the testing process.
Solution Approach 2:
The test device maintains continuous operation by having the counter continuously increase test data and the comparison circuit continuously compare values. This continuity eliminates idle time between test operations, ensuring that the useful action of testing proceeds without interruption, thereby improving reliability assessment efficiency and reducing total test time.
Data Source
AI summary
Provided is a test device performing a test operation on a latch circuit which includes a plurality of latches. The test device includes a counter configured to output test data to a test target latch, selected from among the plurality of latches, in response to a clock signal and increase a value of the test data in response to the clock signal; a comparison circuit configured to receive, as a first input, the test data outputted from the counter, receive, as a second input, test data outputted from the test target latch, and output a comparison signal by comparing the first input with the second input; and a determination circuit configured to generate a defect determination value indicating whether the latch circuit has a defect, based on the comparison signal.