Custom Wrapper Cells for At-Speed Testing of Non-Scannable Elements
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Solution Overview
Problem
Current design for testing (DFT) techniques using dedicated and shared wrapper cells fail to effectively test synchronous inter-core interfaces and non-scannable sequential elements due to limitations such as separate test clocks and undefined logic cones, leading to incomplete test coverage.
Innovation Solution
Implementing custom wrapper cells (CWCs) that operate on the functional clock, allowing at-speed testing of non-scannable sequential elements like embedded memories and clock gating cells, with minimal clock skew delta.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dedicated wrapper cells are used for testing, then test simplicity is improved, but test coverage on synchronous inter-core interfaces deteriorates due to separate test clock being slower than functional clock
Solution Approach 1:
The wrapper cell is segmented into two distinct components: a dedicated test register operating on a separate test clock for simple test control, and a functional interface operating on the functional clock for accurate timing. This segmentation allows each component to operate independently at its optimal clock domain, resolving the contradiction between test simplicity and interface test coverage.
Solution Approach 2:
A dual-clock wrapper cell structure acts as an intermediary between the test clock domain and the functional clock domain. It receives test inputs on the test clock, processes them through the functional interface timing, and outputs test results, thereby enabling delayed fault testing on synchronous interfaces without requiring the entire system to operate at functional speeds.
2Reliability
If shared wrapper cells are used for testing, then at-speed testing capability is improved, but testability of non-scannable sequential elements deteriorates due to undefined logic cones and black box modules
Solution Approach 1:
The wrapper cell is designed with universal functionality to handle both scannable and non-scannable sequential elements. It incorporates a dedicated test register that can capture and hold test patterns for NSEs, along with control logic that can selectively enable or disable the test register based on the element type, thereby providing at-speed testing capability for both categories of elements.
Solution Approach 2:
The dedicated test register performs preliminary action by pre-loading and holding test patterns before they are applied to the functional interface. This allows test data to be prepared and staged in advance at the functional clock speed, ensuring that when the test pattern is applied to NSEs, the timing and setup requirements are already satisfied.
3Measurement precision
If custom wrapper cells are inserted closer to NSEs with tapped clocks, then test accuracy on functional paths is improved, but device complexity increases
Solution Approach 1:
The wrapper cell merges the test register, clock tapping logic, and functional interface control into a single integrated unit. By combining these functions that would otherwise be separate components, the design achieves high test accuracy through close placement and direct clock tapping while minimizing the overall device complexity through functional consolidation.
Data Source
AI summary
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for using custom wrapper cells. One of the methods includes receiving a hardware design having one or more functional components. If the hardware design has a functional component that is incompatible with a shared wrapper cell (SWC), a placeholder test register is added on a path to the functional component that is incompatible with a SWC. The placeholder test register is then converted to a custom wrapper cell.