Scribe-Line Delay Circuit for Sequential Testing Without Bus Collisions
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Solution Overview
Problem
Probe testing of electrical devices is costly, and there is a risk of output collision on the data bus when testing multiple devices simultaneously.
Innovation Solution
A testing circuit with a first pad and delay circuits on a substrate's scribe line is used to sequentially trigger and test electrical devices, reducing costs and preventing output collisions by delaying trigger signals and using separate pads for clock, power, and test commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple electrical devices are tested simultaneously, then testing efficiency is improved, but output collision occurs on the data bus
Solution Approach 1:
The patent divides the simultaneous testing process into sequential segments by introducing delay circuits that stagger the testing operations of multiple electrical devices. Each device is triggered at a different time interval, segmenting the原本 simultaneous operation into sequential operations that avoid data bus collision while maintaining high testing throughput
Solution Approach 2:
The delay circuits perform preliminary action by pre-calculating and implementing time delays before the actual testing operation begins. This preliminary timing adjustment ensures that devices are activated in a predetermined sequence, preventing output collision before it can occur
2Reliability
If probe testing is performed on electrical devices, then testing capability is provided, but testing cost increases
Solution Approach 1:
The testing circuit is designed with multi-functionality to perform various testing operations on multiple electrical devices using a single integrated circuit structure. By incorporating delay circuits, sequential control logic, and multiple testing interfaces within one universal testing system, the patent eliminates the need for multiple separate probe testing setups, thereby reducing overall testing cost while maintaining comprehensive testing capability
Solution Approach 2:
The patent uses a standardized testing circuit design that can be replicated and applied to test different electrical devices. The delay circuit architecture and control logic serve as a reusable template that can be copied for various testing scenarios, reducing development and implementation costs compared to custom probe testing solutions
3Reliability
If delay circuits are introduced to sequence trigger signals, then output collision is prevented, but device complexity increases
Solution Approach 1:
The delay circuits are nested within the existing testing circuit architecture, integrating the timing control function directly into the test device structure. This nesting approach allows the delay functionality to be incorporated without requiring separate external timing devices, thereby preventing output collision while minimizing the increase in overall device complexity
Data Source
AI summary
A testing circuit for testing a plurality of electrical devices is provided. The testing circuit includes a first pad and a plurality of delay circuits. The first pad is disposed on a scribe line of a substrate. The first pad is configured to receive a trigger signal to trigger the electrical devices to sequentially perform a testing operation. The electrical devices are disposed on the substrate. The delay circuits are disposed on the scribe line of the substrate. The delay circuits are electrically connected to the first pad. The delay circuits are configured to delay the trigger signal and output the delayed trigger signal to the corresponding electrical devices. The electrical devices sequentially perform the testing operation according to the delayed trigger signal to respectively output a testing result.