Semiconductor Test Interface Circuitry SMU Compliance Testing

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Solution Overview

Problem

Conventional methods for testing semiconductor device test interface circuitry (DIH) are inefficient and lack accuracy, often relying on monitoring device test yield to detect degraded performance, which can lead to false pass results and damage during testing.

Innovation Solution

A method involving the use of a Source Measurement Unit (SMU) to test switches and decoders in DIH by intentionally applying voltage states and detecting alarm signals, and measuring decoupling capacitance using SMU and DPS resources, while disconnected from the DUT, to ensure functionality and compliance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional monitoring of device test yield is used to detect degraded DIH performance, then testing can be performed without additional hardware, but false pass results occur and device damage may happen

Engineering Contradiction:
Improvetesting accuracyVSAvoidfalse pass results and device damage
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by testing the Device Interface Hardware (DIH) before actual device testing occurs. The methodology performs preliminary diagnostics on switches, decoders, and power supply connections using SMU resources to detect degraded performance early, preventing false pass results and device damage during subsequent production testing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses an intermediary approach by introducing a dedicated testing methodology that mediates between the ATE system and the DIH components. The SMU resources act as intermediaries to safely test DIH functionality by applying controlled voltage states and monitoring alarm signals, providing accurate feedback without directly exposing the device under test to potential damage.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If DIH testing is performed using conventional methods, then testing can be conducted with existing ATE resources, but testing efficiency and accuracy are insufficient

Engineering Contradiction:
Improvetesting efficiencyVSAvoidtesting accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent applies universality by enabling ATE SMU resources to perform multiple functions: both their traditional role in device testing and a secondary role in DIH testing. The same SMU resources that test devices can also test the interface hardware, eliminating the need for separate dedicated testing equipment and improving overall system productivity while maintaining high measurement precision through intentional voltage state application and alarm signal detection.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Measurement precision

If switches and decoders in DIH are tested using conventional approaches, then testing can be performed without disconnecting the device, but testing accuracy is reduced and device risk increases

Engineering Contradiction:
Improveswitch testing accuracyVSAvoidtesting procedure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the testing process into distinct phases: first disconnecting the device under test from the DIH, then testing the DIH components (switches, decoders, power supply) independently using SMU resources, and finally reconnecting the device. This segmentation isolates the DIH testing from device testing, enabling high measurement precision for switch functionality while managing procedure complexity through clear procedural steps.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12360162B2Method for semiconductor device interface circuitry functionality and compliance testing
Publication Date: 2025.07.15 CELERINT LLC
  • US12360162B2 patent drawing
  • US12360162B2 patent drawing
  • US12360162B2 patent drawing

AI summary

A method is provided for determining a decoupling capacitance of a device under test (DUT) interface circuitry, which is between automated testing equipment (ATE) and a DUT. The method: disconnects the DUT from the DUT interface circuitry; connects a Device Under Testing Power Supply (DPS) resource as a DUT Power Supply to the DUT interface circuitry; sets a current clamp of the DPS resource to a test application level; turns off the DPS resource voltage; sets the DPS resource to a force voltage mode; sets the current clamp to a minimum current level; turns on the output; waits a period of time to allow the decoupling capacitance to charge; places the DPS resource into a voltage measurement mode; adds any delay time to the period of time; measures the voltage before the capacitance is fully charged; and determines the decoupling capacitance.