Hierarchical IC Test Pattern Validation Without Full Netlist Simulation
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Solution Overview
Problem
The challenge in testing integrated circuits lies in the inability to directly access inputs and outputs of components within the circuit during manufacturing, as testing is performed through input/output pins, complicating the validation of test patterns in complex hierarchical designs.
Innovation Solution
A method is introduced to validate test patterns by propagating block-level stimuli and responses through a hierarchical design, using sub-block models to compare signals at sub-block inputs and outputs, thereby reducing the need for full simulation of sub-block netlists and allowing earlier validation of test patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full simulation of sub-block netlists is performed to validate test patterns, then validation accuracy is improved, but simulation runtime and memory requirements increase significantly
Solution Approach 1:
The patent segments the validation process into two distinct phases: (1) propagating block-level test stimuli through the block-level design to generate expected sub-block inputs, and (2) comparing these generated inputs against actual sub-block test inputs. This segmentation allows validation without requiring full simulation of the entire hierarchical design, thereby reducing simulation runtime while maintaining validation accuracy.
Solution Approach 2:
The patent extracts and validates only the critical signal propagation paths from block-level inputs to sub-block inputs, rather than simulating the entire netlist. By taking out only the necessary validation components (block-level design, test stimuli, and sub-block input comparisons), the method achieves validation with reduced computational resources and time.
2Measurement precision
If full simulation of sub-block netlists is performed to validate test patterns, then validation accuracy is improved, but memory requirements increase significantly
Solution Approach 1:
The validation process is segmented to load and process only the block-level design and test stimuli in memory, rather than loading the entire sub-block netlist. This segmentation reduces the quantity of data stored in memory while maintaining the ability to validate test patterns accurately through selective signal propagation and comparison.
3Productivity
If test patterns are validated at the block-level using ported stimuli, then validation speed is improved, but the ability to detect errors in sub-block interfaces may worsen
Solution Approach 1:
The patent incorporates a feedback mechanism where the propagated block-level test stimuli are systematically compared against the actual sub-block test inputs. This comparison provides feedback that verifies whether the ported test patterns correctly represent the intended sub-block inputs, thereby maintaining error detection capability while achieving faster validation through block-level processing.
Solution Approach 2:
The patent replaces the mechanical system of full netlist simulation with a simplified signal propagation model at the block-level. By substituting detailed sub-block netlist analysis with block-level design propagation and comparison, the method achieves faster validation while preserving error detection through the comparison step that verifies interface signal integrity.
Data Source
AI summary
A block of circuitry contains at least one sub-block. Test patterns for the sub-block (sub-level test patterns) include sub-level test stimuli and corresponding sub-level test responses. These are ported to the block-level to produce block-level test patterns, block-level test stimuli, and block-level test responses. The block-level test patterns are validated as follows. Propagation of the block-level test stimuli through the block-level design is computed. The signals produced by such computed propagation at the sub-block inputs are compared against the sub-level test stimuli, and the signals produced by such computed propagation at the block outputs are compared against the block-level test responses.