Functional Circuit Block Harvesting via Programmable Gating
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits (ICs) with increased functionality face challenges in efficiently utilizing various functional circuit blocks across diverse platforms due to varying requirements, leading to inefficiencies in power consumption and potential adverse circuit interactions.
Innovation Solution
The ICs are configured with programmable registers that enable selective disabling of functional circuit blocks based on testing results and platform needs, using power and clock gating to optimize power usage and prevent unwanted signal interactions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple functional circuit blocks are integrated into a single IC to increase functionality, then the IC can support diverse platforms and applications, but power consumption increases and adverse circuit interactions may occur
Solution Approach 1:
The IC is divided into multiple independently controllable functional circuit blocks, each with its own power and clock gating mechanisms. This segmentation allows selective activation of only the necessary blocks for a given platform, reducing overall power consumption while maintaining the ability to support diverse applications.
Solution Approach 2:
The patent implements dynamic power and clock gating mechanisms that can selectively enable or disable functional circuit blocks based on platform requirements. This dynamic control allows the IC to adapt its power consumption profile to match the specific needs of different platforms, resolving the contradiction between versatility and energy efficiency.
2Device complexity
If multiple functional circuit blocks are integrated into a single IC, then system integration increases, but static power consumption increases
Solution Approach 1:
The IC architecture segments functional circuit blocks into independently controllable units, each with dedicated power gating. This allows the system to maintain high integration complexity while preventing static power consumption from scaling linearly with the number of blocks, as only active blocks consume static power.
Solution Approach 2:
The patent extracts power control functionality by introducing separate power gating circuits for each functional block. This extraction allows the main IC logic to remain highly integrated while the power management is handled independently, reducing static power consumption by completely powering down unused blocks.
3Adaptability or versatility
If all functional circuit blocks are enabled by default, then platform adaptability is maximized, but unwanted signal interactions and spurious noise increase
Solution Approach 1:
The IC is segmented into independently controllable functional blocks with separate clock gating mechanisms. This segmentation allows the system to enable only the necessary blocks for a given platform, preventing unwanted signal interactions and spurious noise from inactive blocks while preserving the ability to support multiple platforms.
Solution Approach 2:
The patent implements dynamic clock gating that can selectively disable clocks to functional circuit blocks based on platform requirements. This dynamic approach prevents spurious noise and unwanted signal interactions from inactive blocks while maintaining platform adaptability, as the clock gating can be reconfigured for different platforms.
Data Source
AI summary
An integrated circuit (IC) configurable for use in one of a number of possible platforms is disclosed. The IC includes a number of different functional circuit blocks and a plurality of programmable register. The programmable registers, when programmed, can cause corresponding functional circuit blocks to be fully or partially disabled. The different platforms support different sets of peripherals. The IC is thus configured, using the programmable registers, for use in a particular platform to support its corresponding set of peripherals, while another instance of the IC may be configured for use in another platform, supporting its particular set of peripherals.


