3D Stacked Flash Memory Array With Cut-Off Gate Line
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Solution Overview
Problem
Conventional 3D flash memory arrays face limitations in achieving high integrity and uniform electrical properties due to the formation of control gates and word lines, which also increase fabrication costs and reduce operating speed.
Innovation Solution
A 3D stacked flash memory array with a cut-off gate line is fabricated using a single crystal substrate, featuring insulator and semiconductor strips with trenches, a cut-off gate line, and multiple word lines stacked with insulating layers, allowing two memory cells to be operated by each word line, reducing fabrication costs and enhancing integrity and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If control gates and word lines are formed in each memory cell, then memory cell operation is enabled, but fabrication cost increases and operating speed decreases
Solution Approach 1:
The gate structure is segmented into a cut-off gate line at the bottom and multiple word lines stacked above it. This segmentation allows the cut-off gate line to serve as a common control for multiple memory cells, eliminating the need for separate control gates in each cell, thereby reducing fabrication cost and improving operating speed.
Solution Approach 2:
The cut-off gate line performs a universal function by serving as a common control gate for multiple memory cells simultaneously. Instead of each memory cell having its own dedicated control gate, the cut-off gate line controls multiple cells, reducing the total number of control gates needed and simplifying the fabrication process.
2Reliability
If control gates are formed per memory cell, then memory cell control is achieved, but integrity degree is limited
Solution Approach 1:
Multiple control functions are merged into a single cut-off gate line structure. By combining the control functionality for multiple memory cells into one gate line, the device complexity is reduced while maintaining or improving the integrity degree through more uniform electrical properties.
Solution Approach 2:
The gate structure transitions from a planar arrangement to a three-dimensional stacked configuration. The cut-off gate line is positioned at the bottom with word lines stacked vertically above it, utilizing the vertical dimension to reduce the number of control gates needed while improving signal uniformity and integrity across multiple memory cells.
3Ease of operation
If multiple control gates are formed, then memory cell control is improved, but fabrication cost increases
Solution Approach 1:
The redundant control gate structures are extracted and removed from the design. By taking out the unnecessary control gates that would normally be formed in each memory cell and replacing them with a single cut-off gate line, fabrication cost is reduced while memory cell control functionality is maintained through the stacked word line configuration.
Data Source
AI summary
A three-dimensional stacked flash memory array having cut-off gate line and a fabricating method of the same are provided. The flash memory array enables to operate two memory cells by each word line, to produce a high integrity without limitation by vertical stacks of word lines, to increase operating speed and uniformity of electrical property between cells by using a single crystal substrate as a channel region, and to reduce a fabricating cost to a great amount by a fabricating method which is including steps of forming a plurality of trenches in a semiconductor substrate and stacking repeatedly a conductive material interlaid with an insulating layer from bottom of each trench to form a cut-off gate line and a plurality of word lines.