3D Stacked Semiconductor Devices with Folded Data Paths
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Solution Overview
Problem
The management of wire delay and spatial constraints in semiconductor devices poses challenges as processors become more complex, hindering efficient data paths and overall performance due to increased physical distances and space limitations.
Innovation Solution
A 3D stacked semiconductor device with integrated folded data paths, where data sources and execution units are vertically aligned to minimize physical distance and optimize data communication, utilizing a 3D configuration to enhance efficiency and reduce wire delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If more functional units and data storage elements are integrated into the processor, then the processor capability is improved, but the wire delay increases due to increased physical distances
Solution Approach 1:
The patent transitions from a planar 2D layout to a 3D stacked architecture, utilizing the vertical dimension to place functional units and data storage elements at different heights. This dimensional change allows components to be positioned closer together physically, reducing wire delay while accommodating more functional units within the same footprint.
Solution Approach 2:
The patent implements a nested structure where functional units and data storage elements are integrated across multiple stacked dies. The data path is folded to navigate through the vertical stack, with signals routing through intermediate layers that contain both functional units and storage elements, creating a compact nested arrangement that reduces overall path length.
2Productivity
If more functional units are added to increase processor capability, then the processor performance is improved, but the physical footprint increases due to space constraints
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple dies containing functional units and data storage elements. This 3D arrangement allows significantly more functional units to be packed into a smaller physical footprint compared to traditional planar integration, as the stack extends in the vertical direction rather than expanding laterally.
Solution Approach 2:
The patent merges functional units and data storage elements into an integrated 3D stack where both types of components coexist across multiple layers. This combining of functions within the same spatial volume (vertical stack) maximizes processor capability while minimizing the overall physical footprint.
3Speed
If data sources and execution units are vertically aligned to reduce wire delay, then the data transfer speed is improved, but the device complexity increases
Solution Approach 1:
The patent performs preliminary routing configuration during the manufacturing process, where data paths are pre-formed to connect vertically aligned data sources and execution units across stacked dies. This preliminary action of establishing fixed vertical connections during fabrication simplifies the final device operation, as the optimized paths are built-in rather than requiring complex dynamic routing.
Solution Approach 2:
The patent segments the data path into discrete vertical segments across multiple stacked dies, with each segment connecting adjacent layers. This segmentation allows the complex 3D routing problem to be broken down into simpler 2D connections between layers, reducing the overall device complexity by modularizing the data path structure.
Data Source
AI summary
Apparatuses, systems, and methods relating to three-dimensional stacked semiconductor devices with integrated folded data paths for enhanced wire delay optimization are described. In one example, a semiconductor device includes a first die and a second die. The first die can include a data source, and the second die can include an execution unit. The second die is oriented in a common plane with the first die and positioned relative to the first die in a vertical dimension perpendicular to an orientation of the common plane. The semiconductor device can also include a data path that electrically couples the data source and the execution unit. Various additional apparatuses, systems, and methods are disclosed.